TL16C2752 Datasheet, PDF (8/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
SLWS188 – JUNE 2006
Internal ⁸
Data Bus
9−2
D(7 − 0)
Data
Bus
Buffer
S
e
l
e
c
8
t
Receiver
Buffer
Register
Receiver
FIFO
Receiver
Shift
Register
IrDA Decoder
11
XTAL1
XTAL2 ¹³
10
A0
A1 ¹⁴
A2 ¹⁵
Crystal
OSC
Buffer
CS ¹⁸
16
CHSEL
RESET ²¹
24
IOR
IOW ²⁰
TXRDYA ¹
MFA ³⁵
TXRDYB ³²
MFB ¹⁹
Select
and
Control
Logic
INTA, B
34, 17
Line
Control
Register
Divisor
Latch (LS)
Divisor
Latch (MS)
Line
Status
Register
Transmitter
Holding
Register
Modem
Control
Register
Modem
Status
Register
Baud
Generator
Transmitter
S
FIFO
e
l
8
e
c
t
8
8
Receiver
Timing and
Control
Transmitter
Timing and
Control
Transmitter
8
Shift
Register
IrDA Encoder
Modem
Control
Logic
V_CC ^{33, 44}
GND ^{12, 22}
Power
Supply
Interrupt
Enable
Register
8 ^Interrupt
Control
Logic
Interrupt
8
Identification
Register
FIFO
Control
Register
A. Pin numbers shown are for 44-pin PLCC FN package.
Figure 4. Functional Block Diagram
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39, 25
RXA, B
36, 23
RTSA, B
Autoflow
Control
(AFE)
38, 26
TXA, B
40, 28
37, 27
41, 29
42, 30
43, 31
CTSA, B
DTRA, B
DSRA, b
CDA,B
RIA, B
8
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