TL16C2752 Datasheet, PDF (4/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
SLWS188 – JUNE 2006
TL16C2752 Block Diagram
www.ti.com
A2 − A0
D7 − D0
CS
CHSEL
IOR
IOW
INTA
INTB
TXRDYA
TXRDYB
MFA
MFB
RESET
Data Bus
Interface
UART Channel A
64 Byte Tx FIFO
Tx
IR ENC
BAUD
Rate
Gen
UART Regs
64 Byte Rx FIFO
Rx
IR DEC
UART Channel B
64 Byte Tx FIFO
Tx
IR ENC
BAUD
Rate
Gen
UART Regs
64 Byte Rx FIFO
Rx
IR DEC
TXA
CTSA
DTRA
DSRA, RIA, CDA
RTSA
RXA
TXB
CTSB
DTRB
DSRB, RIB, CDB
RTSB
RXB
XTAL1
XTAL2
Crystal
OSC
Buffer
A. MF output allows selection of OP, BAUDOUT, or RXRDY per channel.
V_CC
GND
DEVICE INFORMATION
NAME
A0
A1
A2
TERMINAL
FN NO. RHB NO.
10
3
14
6
15
7
CDA, CDB 42, 30
–
CHSEL
16
8
CS
18
10
CTSA,
CTSB
40, 28 25, 17
TERMINAL FUNCTIONS
I/O DESCRIPTION
I Address 0 select bit. Internal registers address selection
I Address 1 select bit. Internal registers address selection
I Address 2 select bit. Internal registers address selection
Carrier detect (active low). These inputs are associated with individual UART channels A and
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B. A low on these pins indicates that a carrier has been detected by the modem for that
channel. The state of these inputs is reflected in the modem status register (MSR). These
inputs should be pulled high if unused.
Channel select. UART channel A or B is selected by the state of this pin when CS is a logic 0.
A logic 0 on the CHSEL selects the UART channel B while a logic 1 selects UART channel A.
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CHSEL could just be an address line from the user CPU such as A3. Bit 0 of the alternate
function register (AFR) can temporarily override CHSEL function, allowing the user to write to
both channel register simultaneously with one write cycle when CS is low. It is especially
useful during the initialization routine.
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UART chip select (active low). This pin selects channel A or B in accordance with the state of
the CHSEL pin. This allows data to be transferred between the user CPU and the 2552.
Clear to send (active low). These inputs are associated with individual UART channels A and
B. A logic low on the CTS pins indicates the modem or data set is ready to accept transmit
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data from the 2552. Status can be tested by reading MSR bit 4. These pins only affect the
transmit and receive operations when auto CTS function is enabled through the enhanced
feature register (EFR) bit 7, for hardware flow control operation. These inputs should be
pulled high if unused.
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