TL16C2752 Datasheet, PDF (13/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
www.ti.com
SLWS188 – JUNE 2006
RECEIVER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) ⁽¹⁾
PARAMETER
td12 Delay time, RCLK to sample
td13 Delay time, stop to set INT or read RBR to LSI
interrupt or stop to RXRDY↓
td14 Delay time, read RBR/LSR to reset INT
td26 Delay time, RCV threshold byte to RTS↑
td27 Delay time, read of last byte in receive FIFO to
RTS↓
td28 Delay time, first data bit of 16th character to RTS↑
td29 Delay time, RBRRD low to RTS↓
ALT.
SYMBOL
tSCD
tSINT
tRINT
FIGURE
9
8, 9, 10,
11, 12
8, 9, 10,
11, 12
19
19
20
20
TEST
CONDITIONS
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
1.8 V
MIN MAX
20
1
LIMITS
2.5 V
3.3 V
5V
MIN MAX MIN MAX MIN MAX
15
10
10
1
1
1
100
90
80
70
UNIT
ns
RCLK
cycle
ns
2 baudout
cycles ⁽²⁾
2 baudout
cycles
2 baudout
cycles
2 baudout
cycles
(1) In the FIFO mode, the read cycle (RC) = 1 baudclock (min) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
(2) A baudout cycle is equal to the period of the input clock divided by the programmed divider in DLL, DLM.
TRANSMITTER SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
ALT. SYMBOL FIGURE
td15 Delay time, initial write to transmit start
tIRS
td16 Delay time, start to INT
tSTI
td17 Delay time, IOW (WR THR) to reset INT
tHR
td18 Delay time, initial write to INT (THRE⁽¹⁾)
tSI
td19 Delay time, read IOR↑ to reset INT (THRE⁽¹⁾)
tIR
td20 Delay time, write to TXRDY inactive
tWXI
td21 Delay time, start to TXRDY active
tSXA
tSU4 Setup time, CTS↑ before midpoint of stop bit
td25 Delay time, CTS low to TX↓
14
14
14
14
14
15, 16
15, 16
18
18
TEST
CONDITIONS
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
CL = 30 pF
1.8 V
MIN MAX
8
24
8
10
70
16
34
70
60
9
30
24
LIMITS
2.5 V
3.3 V
MIN MAX MIN MAX
8 24
8 24
8 10
8 10
60
50
16 34 16 34
50
35
45
35
9
9
20
10
24
24
5V
UNIT
MIN MAX
8 24 baudout
cycles
8 10 baudout
cycles
50 ns
16 34 baudout
cycles
35 ns
35 ns
9 baudout
cycles
10
ns
24 baudout
cycles
(1) THRE = Transmitter Holding Register Empty; IIR = Interrupt Identification Register.
MODEM CONTROL SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
td22 Delay time, WR MCR to output
td23 Delay time, modem interrupt to set INT
td24 Delay time, RD MSR to reset INT
ALT.
SYMBOL
FIGURE
tMDO
17
tSIM
17
tRIM
17
TEST
CONDITIONS
CL = 30 pF
CL = 30 pF
CL = 30 pF
1.8 V
MIN MAX
90
60
80
LIMITS
2.5 V
3.3 V
MIN MAX MIN MAX
70
60
50
40
60
50
5V
MIN MAX
50
35
40
UNIT
ns
ns
ns
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