TL16C2752 Datasheet, PDF (5/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
www.ti.com
NAME
D0-D4
D5-D7
TERMINAL
FN NO. RHB NO.
2 - 6 27 - 31
7 - 9 32, 1, 2
DSRA,
DSRB
41, 29
–
DTRA,
DTRB
GND
37, 27
–
12, 22
20
INTA, INTB 34, 17 21, 9
IOR
IOW
NC
24
14
20
11
–
18, 19
MFA, MFB 35, 19
–
RESET
21
12
RIA, RIB
43, 31
–
RTSA,
RTSB
36, 23 22, 13
RXA, RXB 39, 25 24, 15
TXA, TXB
TXRDYA,
TXRDYB
38, 26
1, 32
23, 16
–
DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
SLWS188 – JUNE 2006
I/O DESCRIPTION
Data bus (bidirectional). These pins are the eight bit, 3-state data bus for transferring
I/O information to or from the controlling CPU. D0 is the least significant bit and the first data bit in
a transmit or receive serial data stream.
Data set ready (active low). These inputs are associated with individual UART channels A
I
and B. A logic low on these pins indicates the modem or data set is powered on and is ready
for data exchange with the UART. The state of these inputs is reflected in the modem status
register (MSR). These inputs should be pulled high if unused.
Data terminal ready (active low). These outputs are associated with individual UART channels
A and B. A logic low on these pins indicates that theTLl16C2552 is powered on and ready.
O These pins can be controlled through the modem control register. Writing a 1 to MCR bit 0
sets the DTR output to low, enabling the modem. The output of these pins is high after writing
a 0 to MCR bit 0, or after a reset.
Signal and power ground.
Interrupt A and B (active high). These pins provide individual channel interrupts, INT A and B.
INT A and B are enabled when MCR bit 3 is set to a logic 1, interrupt sources are enabled in
O the interrupt enable register (IER). Interrupt conditions include: receiver errors, available
receiver buffer data, available transmit buffer space or when a modem status flag is detected.
INTA-B are in the high-impedance state after reset.
Read input (active low strobe). A high to low transition on IOR will load the contents of an
I internal register defined by address bits A0-A2 onto the TL16C2552 data bus (D0-D7) for
access by an external CPU.
Write input (active low strobe). A low to high transition on IOW will transfer the contents of the
I data bus (D0-D7) from the external CPU to an internal register that is defined by address bits
A0-A2 and CSA and CSB
No internal connection
Multi-function output. This output pin can function as the OP, BAUDOUT, or RXRDY pin. One
of these output signal functions can be selected by the user programmable bits 1-2 of the
alternate function register (AFR). These signal functions are described as follows:
1. OP - When OP (active low) is selected, the MF pin is a logic 0 when MCR bit 3 is set to
a logic 1 (see MCR bit 3). MCR bit 3 defaults to a logic 1 condition after a reset or
O
power-up.
2. BAUDOUT - When BAUDOUT function is selected, the 16× baud rate clock output is
available at this pin.
3. RXRDY - RXRDY (active low) is intended for monitoring DMA data transfers.
If it is not used, leave it unconnected.
Reset. RESET will reset the internal registers and all the outputs. The UART transmitter
I output and the receiver input will be disabled during reset time. See TL16C2552 external
reset conditions for initialization details. RESET is an active-high input.
Ring indicator (active low). These inputs are associated with individual UART channels A and
B. A logic low on these pins indicates the modem has received a ringing signal from the
I telephone line. A low to high transition on these input pins generates a modem status
interrupt, if enabled. The state of these inputs is reflected in the modem status register (MSR).
These inputs should be pulled high if unused.
Request to send (active low). These outputs are associated with individual UART channels A
and B. A low on the RTS pin indicates the transmitter has data ready and waiting to send.
O
Writing a 1 in the modem control register (MCR bit 1) sets these pins to low, indicating data is
available. After a reset, these pins are set to high. These pins only affects the transmit and
receive operation when auto RTS function is enabled through the enhanced feature register
(EFR) bit 6, for hardware flow control operation.
Receive data input. These inputs are associated with individual serial channel data to the
I 2552. During the local loopback mode, these RX input pins are disabled and TX data is
internally connected to the UART RX input internally.
Transmit data. These outputs are associated with individual serial transmit channel data from
O the 2552. During the local loopback mode, the TX input pin is disabled and TX data is
internally connected to the UART RX input.
O
Transmit ready (active low). TXRDY A and B go low when there are at least a trigger level
numbers of spaces available. They go high when the TX buffer is full.
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