TL16C2752 Datasheet, PDF (15/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

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CHSEL,
A2 −A0
CS
IOR
Valid Address
t_d8
t_w7
t_w7
t_h7
t_d13
TL16C2752
SLWS188 – JUNE 2006
Valid Address
t_d8
t_w7
t_h7
t_w7
D7 −D0
t_d10
t_d10
t_d11
Valid Data
Figure 7. Read Cycle Timing Waveforms
t_h11
Valid Data
RCLK
(Internal)
Sample Clock
(Internal)
TL16C450 Mode:
RXA, RXB
Start
Sample Clock
8 CLKs
Data Bits 5− 8
Parity
t_d12
Stop
INT
(data ready)
INT
(RCV error)
IOR
(read RBR)
50%
50%
t_d13
50%
t_d14
50%
50% _Active
IOR
(read LSR)
50%
Active
t_d14
Figure 8. Receiver Timing Waveforms
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