TL16C2752 Datasheet, PDF (6/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
SLWS188 – JUNE 2006
NAME
V_CC
TERMINAL
FN NO. RHB NO.
33, 44
26
XTAL1
11
4
XTAL2
13
5
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DEVICE INFORMATION (continued)
TERMINAL FUNCTIONS (continued)
I/O DESCRIPTION
I Power supply inputs.
Crystal or external clock input. XTAL1 functions as a crystal input or as an external clock
I
input. A crystal can be connected between XTAL1 and XTAL2 to form an internal oscillator
circuit (see Figure 4). Alternatively, an external clock can be connected to XTAL1 to provide
custom data rates.
O
Output of the crystal oscillator or buffered clock. See also XTAL1. XTAL2 is used as a crystal
oscillator output or buffered a clock output.
Detailed Description
Hardware Autoflow Control (see Figure 1)
Hardware Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be
active before the transmitter FIFO can emit data. With auto-RTS, RTS becomes active when the receiver needs
more data and notifies the sending serial device. When RTS is connected to CTS, data transmission does not
occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated using ACE1 and
ACE2 from a TLC16C2752 with the autoflow control enabled. If not, overrun errors can occur when the transmit
data rate exceeds the receiver FIFO read latency.
ACE1
ACE2
D7 −D0
RCV
FIFO
XMT
FIFO
Serial to
Parallel
Flow
Control
Parallel
to Serial
Flow
Control
RX
RTS
TX
CTS
TX
CTS
RX
RTS
Parallel
to Serial
Flow
Control
Serial to
Parallel
Flow
Control
XMT
FIFO
RCV
FIFO
D7 −D0
Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
Auto-RTS (See Figure 2 and Figure 3)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram) and
is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches the defined halt
trigger level 8 (see Figure 3), RTS is deasserted. The sending ACE may send an additional byte after the trigger
level is reached (assuming the sending ACE has another byte to send) because it may not recognize the
deassertion of RTS until after it has begun sending the additional byte. RTS is automatically reasserted once the
defined resume trigger level is reached.
Auto-CTS (See Figure 2)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the last
stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host system.
When flow control is enabled, CTS level changes do not trigger host interrupts because the device automatically
controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the transmit FIFO and
a receiver overrun error may result.
6
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