TL16C2752 Datasheet, PDF (17/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

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TL16C2752
SLWS188 – JUNE 2006
IOR
(RD RBR)
RXA, RXB
(first byte)
Stop
50%
Active
See Note A
Sample Clock
(Internal)
t_d13
(see Note B)
RXRDYA, RXRDYB
50%
t_d14
50%
Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
IOR
(RD RBR)
RXA, RXB
(first byte that reaches
the trigger level)
Sample Clock
(Internal)
t_d13
(see Note B)
RXRDYA, RXRDYB
50%
50%
Active
See Note A
t_d14
50%
Figure 12. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
TXA, TXB
INT
(THRE)
t_d15
50%
t_d17
IOW _50%
(WR THR)
IOR
Start
50%
Data Bits
50%
50%
t_d18
t_d17
50%
50%
Parity
Stop
t_d16
Figure 13. Transmitter Timing Waveforms
Start
50%
50%
50%
t_d19
50%
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