TL16C2752 Datasheet, PDF (21/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
www.ti.com
ADDRESS
A2 - A0
000
000
001
010
000
001
001
010
011
100
101
110
111
111
111
000
001
010
100
101
110
111
Table 1. UART Channel A and B UART Internal Registers
RESET (HEX)
VALUE
COMMENTS
REGISTER
XX
XX
LCR[7] = 0
XX
XX
LCR[7] = 1, LCR ≠ 0xBF
00
00
DLL, DLM = 0x00,
0A
LCR[7] = 1, LCR ≠ 0xBF
00
LCR[7] = 0
01
00
LCR[7] = 0
00
00
60
LCR ≠ 0xBF
X0
FF
LCR ≠ 0xBF, FCTR[6] = 0
00
LCR ≠ 0xBF, FCTR[6] = 1
80
00
00
00
00
00
LCR = 0xBF
00
00
00
16C550 Compatible Registers
RHR = Receive Holding Register
THR - Transmit Holding Register
DLL - Div Latch Low Byte
DLM - Div Latch High Byte
AFR - Alternate Function REgister
DREV - Device Revision Code
DVID - Device Identification Code
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
LCR = Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
Reserved
MSR - Modem Status Register
Reserved
SPR - Scratch Pad Register
FLVL - RX/TX FIFO Level Counter Register
EMSR - Enhanced Mode Select Register
Enhanced Registers
TRG - RX/TX FIFO Trigger Level Register
FC - RX/TX FIFO Level Counter Register
FCTR - Feature Control Register
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
SLWS188 – JUNE 2006
READ/WRITE
Read-only
Write-only
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read/Write
Read-only
Write-only
Read/Write
Read/Write
Read-only
Write-only
Read-only
Write-only
Read/Write
Read-only
Write-only
Write-only
Read-only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Address
A2 - A0
000
000
001
010
010
011
100
101
110
111
111
111
Table 2. Internal Registers Description⁽¹⁾
Reg
NAME
RHR
THR
IER
ISR
FCR
LCR
MCR
LSR
MSR
SPR
EMSR
FLVL
Read/
Write
RD
WR
RD/WR
RD
WR
RD/WR
RD/WR
RD
RD
RD/WR
WR
RD
Comments
Bit 7
Bit 6
Bit 5
Bit 4
16C550 Compatible Registers
LCR[7] = 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 7
Bit 6
Bit 5
Bit 4
0/
0/
0/
0/
CTS Int.
Enable
RTS Int.
Enable
Xoff Int.
Enable
Sleep Mode
Enable
FIFOs
Enabled
FIFOs
Enabled
0/
INT Source
Bit 5
0/
INT Source
Bit 4
RXFIFO
Trigger
RXFIFO
Trigger
0/
TXFIFO
Trigger
0/
TXFIFO
Trigger
LCR ≠ 0xBF
Divisor
Enable
Set TX Break Set Parity
Even Parity
0/
BRG
Prescaler
0/
IR Mode
Enable
0/
XonAny
Internal
Loopback
Enable
RX FIFO
Global Error
THR & TSR
Empty
THR Empty
RX Break
CD# Input
RI# Input
DSR# Input CTS# Input
LCR ≠ 0xBF
FCTR Bit 6 = 0
Bit 7
Bit 6
Bit 5
Bit 4
LDR ≠ 0xBF
FCTR Bit 6 = 1
16X Sampling
Rate Mode
Bit 7
LSR Error
Interrupt
Imd/Dly#
Bit 6
Auto RTS
Hyst. Bit 3
Bit 5
Auto RTS
Hyst Bit 2
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 3
Bit 3
Modem Stat.
Int. Enable
Bit 2
Bit 2
RX Line Stat.
Int. Enable
Bit 1
Bit 1
TX Empty Int.
Enable
Bit 0
Bit 0
RX Data Int.
Enable
INT Source
Bit 3
INT Source
Bit 2
INT Source
Bit 1
INT Source
Bit 0
DMA Mode
Enable
TX FIFO
Reset
RX FIFO
Reset
FIFOs Enable
Parity Enable
OP2# Output
Control
Stop Bits
Rsrvd (OP1#)
Word Length
Bit 1
RTS# Output
Control
Word Length
Bit 0
DTR# Output
Control
RX Framing
Error
Delta CD#
Bit 3
Auto RS485
Output
Inversion
Bit 3
RX Parity
Error
Delta RI#
Bit 2
Rsrvd
Bit 2
RX Overrun
Error
Delta DSR#
Bit 1
RX Data
Ready
Delta CTS#
Bit 0
Rx/Tx FIFO
Count
Rx/Tx FIFo
Count
Bit 1
Bit 0
(1) Shaded bits are accessible when EFR Bit 4 = 1.
Submit Documentation Feedback
21