TL16C2752 Datasheet, PDF (16/25 Pages) Texas Instruments – 1.8-V to 5-V DUAL UART WITH 64-BYTE FIFOS

TL16C2752
SLWS188 – JUNE 2006
www.ti.com
RXA, RXB
Sample Clock
(Internal)
Trigger Level
INT
(FCR6, 7 = 0, 0)
INT
Line Status
Interrupt (LSI)
IOR
(RD LSR)
IOR
(RD RBR)
Data Bits 5 −8
Stop
50%
50%
t_d13
(see Note A)
50%
t_d14
50%
t_d14
Active
50%
Active
50%
Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms
(FIFO at or above
trigger level)
(FIFO below
trigger level)
RXA, RXB
Sample Clock
(Internal)
Time-Out or
Trigger Level
Interrupt
Line Status
Interrupt (LSI)
IOP
(RD LSR)
Stop
50%
t_d13
(see Note A)
t_d14
50%
Top Byte of FIFO
50%
t_d13
t_d14
50%
50%
(FIFO at or above
trigger level)
(FIFO below
trigger level)
IOR
(RD RBR)
Active 50%
50%
Active
Previous Byte
Read From FIFO
Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
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