DAC8718 Datasheet, PDF (5/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
www.ti.com
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at T_A = T_MIN to T_MAX, AV_DD = +16.5V, AV_SS = –16.5V, IOV_DD = DV_DD = +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values ⁽¹⁾,
unless otherwise noted.
DAC8718
PARAMETER
OFFSET DAC OUTPUT^{(15) (16)}
CONDITIONS
MIN
TYP
MAX
UNIT
Voltage output
Full-scale error
Zero-code error
Linearity error
V_REF = +5V
T_A = +25°C
T_A = +25°C
0
±4
±2
±6
5
V
LSB
LSB
LSB
Differential linearity error
±1
LSB
ANALOG MONITOR PIN (V_MON)
Output impedance⁽¹⁷⁾
Three-state leakage current
T_A = +25°C
2
kΩ
100
nA
AUXILIARY ANALOG INPUT
Input range
Input impedance
(AIN-x to V_MON)
Input capacitance⁽¹⁵⁾
T_A = +25°C
AV_SS
AV_DD
V
2
kΩ
4
pF
Input leakage current
30
nA
REFERENCE INPUT
Reference input voltage range⁽¹⁸⁾
1.0
5.5
V
Reference input dc impedance
Reference input capacitance⁽¹⁵⁾
DIGITAL INPUT⁽¹⁵⁾
10
MΩ
10
pF
High-level input voltage, V_IH
Low-level input voltage, V_IL
Input current
IOV_DD = +4.5V to +5.5V
IOV_DD = +2.7V to +3.3V
IOV_DD = +1.7V to 2.0V
IOV_DD = +4.5V to +5.5V
IOV_DD = +2.7V to +3.3V
IOV_DD = +1.7V to 2.0V
CLR, LDAC, RST, CS, and SDI
USB/BTC, RSTSEL, and GPIO-n
3.8
2.3
1.5
–0.3
–0.3
–0.3
0.3 + IOV_DD
V
0.3 + IOV_DD
V
0.3 + IOV_DD
V
0.8
V
0.6
V
0.3
V
±1
μA
±5
μA
CLR, LDAC, RST, CS, and SDI
5
pF
Input capacitance
USB/BTC and RSTSEL
12
pF
DIGITAL OUTPUT⁽¹⁵⁾
GPIO-n
14
pF
High-level output voltage, V_OH
(SDO)
Low-level output voltage, V_OL
(SDO)
GPIO-n output voltage low, V_OL
GPIO-n output voltage high, V_OH
High-impedance leakage current
IOV_DD = +2.7V to +5.5V, sourcing 1mA
IOV_DD = +1.8V, sourcing 200μA
IOV_DD = +2.7V to +5.5V, sinking 1mA
IOV_DD = +1.8V, sinking 200μA
1mA sink from IOV_DD
10kΩ pull-up resistor to IOV_DD
SDO and GPIO-n
IOV_DD – 0.4
1.6
0
0
0.99 × IOV_DD
0.15
±5
IOV_DD
V
IOV_DD
V
0.4
V
0.2
V
V
V
μA
High-impedance output
capacitance
SDO
GPIO-n
5
pF
14
pF
(15) Specified by design.
(16) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±10 LSB from the nominal number listed in Table 7. The Offset DAC pins are not intended to drive an external load, and
must not be connected during dual-supply operation.
(17) 8kΩ when V_MON is connected to Reference Buffer A or B, and 4kΩ when V_MON is connected to Offset DAC-A or -B.
(18) Reference input voltage ≤ DV_DD.
Copyright © 2009, Texas Instruments Incorporated
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