 English |
|
|
|
|
|
|
|
| DAC8718 Datasheet, PDF (14/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER | |||
| |||
| ◁ |
DAC8718
SBAS467A â MAY 2009 â REVISED DECEMBER 2009
www.ti.com
TIMING DIAGRAMS (continued)
Case 3: Daisy-Chain Mode: Update without LDAC pin; LDAC pin tied to logic low.
CS
SCLK
SDI
SDO
t8
t4
t1
Hi-Z
t2
t3
BIT 23 (N)
t13
t5
t6
BIT 22 (N)
Input Data Register and
t7
DAC Latch Updated
When Correction Completes(1)
BIT 0 (N) BIT 23 (N+1) BIT 0 (N+1)
t11
BIT 23 (N)
t12
Hi-Z
BIT 0 (N)
Low
LDAC
NOTE: (1) If the correction engine is off, the DAC latch is reloaded immediately after the DAC Data Register is updated.
Case 4: Daisy-Chain Mode: Update with LDAC pin.
t8
t4
CS
SCLK
SDI
SDO
Hi-Z
t1
t2
t3
BIT 23 (N)
t13
t5
t6
BIT 22 (N)
BIT 0 (N) BIT 23 (N+1)
t11
BIT 23 (N)
Input Data Register Updated,
t7 but DAC Latch is Not Updated
BIT 0 (N+1)
t12
BIT 0 (N)
Hi-Z
LDAC
High
t9
t10
DAC Latch Updated(2)
NOTE: (2) The DAC latch is updated when LDAC goes low. The proper data are loaded if the t9 timing requirement is satisfied.
Otherwise, invalid data are loaded.
Case 5: Daisy-Chain Mode: Sleeping.
CS
SCLK
SDI
SDO
t14
Hi-Z
DB23
First Word
DB23
DB0
DB0
DB23
Hi-Z
DB23
Last Word
DB0
Hi-Z
DB0
= Donât Care
Bit 23 = MSB
Bit 0 = LSB
Figure 3. SPI Timing for Daisy-Chain Mode
14
Submit Documentation Feedback
Product Folder Link(s): DAC8718
Copyright © 2009, Texas Instruments Incorporated
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese