DAC8718 Datasheet, PDF (42/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
www.ti.com
POWER-ON RESET
The DAC8718 contains a power-on reset circuit that controls the output during power-on and power down. This
feature is useful in applications where the known state of the DAC output during power-on is important. The
Offset DAC Registers, DAC Data Registers, and DAC latches are loaded with the value defined by the RSTSEL
pin, as shown in Table 7. The Gain Registers and Zero Registers are loaded with default values. The Input Data
Register is reset to 0000h, independent of the RSTSEL state.
Table 7. Bipolar Output Reset Values for Dual Power-Supply Operation
RSTSEL PIN
DGND
IOV_DD
DGND
IOV_DD
USB/BTC PIN
DGND
DGND
IOV_DD
IOV_DD
INPUT FORMAT
Straight Binary
Straight Binary
Twos Complement
Twos Complement
VALUE OF DAC
DATA REGISTER
AND DAC LATCH
0000h
8000h
8000h
0000h
VALUE OF OFFSET
DAC REGISTER
FOR GAIN = 6⁽¹⁾
999Ah
999Ah
199Ah
199Ah
V_OUT
–Full-Scale
0V
–Full-Scale
0V
(1) Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the error for symmetrical output. The default value may vary
no more than ±10 LSB from the nominal number listed in this table.
In single-supply operation, the Offset DAC is turned off and the output is unipolar. The power-on reset is defined
as shown in Table 8.
Table 8. Unipolar Output Reset Values for Single Power-Supply Operation
RSTSEL PIN
DGND
IOV_DD
DGND
IOV_DD
USB/BTC PIN
DGND
DGND
IOV_DD
IOV_DD
INPUT FORMAT
Straight Binary
Straight Binary
Twos Complement
Twos Complement
VALUE OF DAC DATA
REGISTER AND DAC
LATCH
0000h
8000h
8000h
0000h
V_OUT
0V
Midscale
0V
Midscale
HARDWARE RESET
When the RST pin is low, the device is in hardware reset. All the analog outputs (V_OUT-0 to V_OUT-7), the DAC
registers, and the DAC latches are set to the reset values defined by the RSTSEL pin as shown in Table 7 and
Table 8. In addition, the Gain and Zero Registers are loaded with default values, communication is disabled, and
the signals on CS and SDI are ignored (note that SDO is in a high-impedance state). The Input Data Register is
reset to 0000h, independent of the RSTSEL state. On the rising edge of RST, the analog outputs (V_OUT-0 to
V_OUT-7) maintain the reset value as defined by the RSTSEL pin until a new value is programmed. After RST
goes high, the serial interface returns to normal operation. CS must be set to a logic high whenever RST is used.
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