DAC8718 Datasheet, PDF (12/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
www.ti.com
PIN
NAME
DV_DD
DGND
DGND
GPIO-1
GPIO-0
AV_SS
V_OUT-7
OFFSET-B
AGND-B
AGND-B
V_OUT-6
V_OUT-5
REF-B
V_OUT-4
AIN-1
AV_DD
USB/BTC
RSTSEL
DGND
IOV_DD
DV_DD
SCLK
CS
SDI
SDO
LDAC
WAKEUP
NC
PIN NO.
QFN-48
TQFP-64
17
24
20
25
22
28
23
29
24
30
26
37
27
38
28
39
29
40
30
41
31
42
32
43
33
44
34
45
35
46
36
48
37
50
38
51
40
54
41
55
42
56
43
57
44
58
45
59
46
61
47
62
48
63
16, 18, 19,
21, 25, 39
2, 13,
15-18, 22,
23, 26, 27,
31-36, 47,
49, 52, 53,
60, 64
PIN DESCRIPTIONS (continued)
I/O
DESCRIPTION
I Digital power supply
I Digital ground
I Digital ground
I/O
General-purpose digital input/output 1. This pin is a bidirectional digital input/output, open-drain and
requires an external resistor. See the GPIO Pins section for details.
I/O
General-purpose digital input/output 0. This pin is a bidirectional digital input/output, open-drain and
requires an external resistor. See the GPIO Pins section for details.
I Negative analog power supply
O DAC-7 output
O
OFFSET DAC-B analog output. Must be connected to AGND-B during single-supply operation
(AV_SS = 0V).
I
Group B⁽¹⁾ analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
I Group B analog ground and the ground of REF-B. This pin must be tied to AGND-A and DGND.
O DAC-6 output
O DAC-5 output
I Group B reference input
O DAC-4 output
I Auxiliary analog input 1, directly routed to the analog mux
I Positive analog power supply
Data format selection of Input DAC data and Offset DAC data. Data are in straight binary format
I when connected to DGND or in twos complement format when connected to IOV_DD. The command
data are always in straight binary format. Refer to Input Data Format section for details.
I
Output reset selection. Selects the output voltage on the V_OUT pin after power-on or hardware reset.
Refer to the Power-On Reset section for details.
I Digital ground
I Interface power
I Digital power supply
I SPI bus serial clock input
I
SPI bus chip select input (active low). Data are not clocked into SDI unless CS is low. When CS is
high, SDO is in a high-impedance state and the SCLK and SDI signals are blocked from the device.
I SPI bus serial data input
SPI bus serial data output.
O
When the DSDO bit = '0', the SDO pin works as an output in normal operation.
When the DSDO bit = '1', SDO is always in a Hi-Z state, regardless of the CS pin status. Refer to
the Timing Diagrams section for details.
Load DAC latch control input (active low). When LDAC is low, the DAC latch is transparent and the
contents of the DAC Data Register are transferred to it. The DAC output changes to the
I
corresponding level simultaneously when the DAC latch is updated. See the Updating the DAC
Outputs section for details. If asynchronous mode is desired, LDAC must be permanently tied low
before power is applied to the device. If synchronous mode is desired, LDAC must be logic high
during power-on.
I
Wake-up input (active low). Restores the SPI from sleep to normal operation. See the Daisy-Chain
Operation section for details.
— Not connected
12
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