DAC8718 Datasheet, PDF (4/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
www.ti.com
ELECTRICAL CHARACTERISTICS: Dual-Supply (continued)
All specifications at T_A = T_MIN to T_MAX, AV_DD = +16.5V, AV_SS = –16.5V, IOV_DD = DV_DD = +5V, REF-A and REF-B = +5V,
gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values ⁽¹⁾,
unless otherwise noted.
DAC8718
PARAMETER
ANALOG OUTPUT (V_OUT-0 to V_OUT-7)⁽⁴⁾
Voltage output⁽⁵⁾
V_REF = +5V
V_REF = +1.5V
Output impedance
Code = 8000h
Short-circuit current⁽⁶⁾
CONDITIONS
MIN
TYP
–15
–4.5
±8
MAX
+15
+4.5
0.5
UNIT
V
V
Ω
mA
Load current
See Figure 37
±3
mA
Output drift vs time
Capacitive load stability
T_A = +25°C, device operating for 500 hours, full-scale output
T_A = +25°C, device operating for 1000 hours, full-scale output
3.4
ppm of FSR
4.3
ppm of FSR
500
pF
To 0.03% of FSR, C_L = 200pF, R_L= 10kΩ, code from 0000h
to FFFFh and FFFFh to 0000h
10
μs
Settling time
To 1 LSB, C_L = 200pF, R_L = 10kΩ, code from 0000h to
FFFFh and FFFFh to 0000h
15
μs
Slew rate ⁽⁷⁾
Power-on delay⁽⁸⁾
Power-down recovery time
Digital-to-analog glitch⁽⁹⁾
To 1 LSB, C_L = 200pF, R_L = 10kΩ, code from 7F00h to
8100h and 8100h to 7F00h
From IOV_DD ≥ +1.8V and DV_DD ≥ +2.7V to CS low
Code from 7FFFh to 8000h and 8000h to 7FFFh
6
μs
6
V/μs
200
μs
60
μs
4
nV-s
Glitch impulse peak amplitude
Channel-to-channel isolation⁽¹⁰⁾
DAC-to-DAC crosstalk⁽¹¹⁾
Digital crosstalk⁽¹²⁾
Digital feedthrough⁽¹³⁾
Code from 7FFFh to 8000h and 8000h to 7FFFh
V_REF = 4V_PP, f = 1kHz
DACs in the same group
DACs among different groups
5
mV
88
dB
7.5
nV-s
1
nV-s
1
nV-s
1
nV-s
Output noise
Power-supply rejection⁽¹⁴⁾
T_A = +25°C at 10kHz, gain = 6
T_A = +25°C at 10kHz, gain = 4
0.1Hz to 10Hz, gain = 6
AV_DD = ±15.5V to ±16.5V
200
130
20
0.05
nV/√Hz
nV/√Hz
μV_PP
LSB
(4) Specified by design.
(5) The analog output range of V_OUT-0 to V_OUT-7 is equal to (6 × V_REF – 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of
the analog output must not be greater than (AV_DD – 0.5V), and the minimum value must not be less than (AV_SS + 0.5V). All
specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted.
(6) When the output current is greater than the specification, the current is clamped at the specified maximum value.
(7) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale.
(8) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid
digital communication.
(9) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as
the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format.
(10) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the
sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale.
(11) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and
subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s.
(12) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input
register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s.
(13) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of
the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s.
(14) The output must not be greater than (AV_DD – 0.5V) and not less than (AV_SS + 0.5V).
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