DAC8718 Datasheet, PDF (45/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
www.ti.com
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
SERIAL INTERFACE
The DAC8718 is controlled over a versatile, three-wire serial interface that operates at clock rates of up to
50MHz and is compatible with SPI, QSPI™, Microwire™, and DSP™ standards.
SPI Shift Register
The SPI Shift Register is 24 bits wide. Data are loaded into the device MSB first as a 24-bit word under the
control of the serial clock input, SCLK. The SPI Shift Register consists of a read/write bit, five register address
bits, 16 data bits, and two reserve bits for future devices, as shown in Table 9. The falling edge of CS starts the
communication cycle. The data are latched into the SPI Shift Register on the falling edge of SCLK while CS is
low. When CS is high, the SCLK and SDI signals are blocked and the SDO pin is in a high-impedance state. The
contents of the SPI shifter register are decoded and transferred to the proper internal registers on the rising edge
of CS. The timing for this operation is shown in the Timing Diagrams section.
The serial interface works with both a continuous and non-continuous serial clock. A continuous SCLK source
can only be used if CS is held low for the correct number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used and CS must be taken high after the final clock in
order to latch the data.
The serial interface requires CS to be logic high during the power-on sequencing; therefore, it is advised to have
a pullup resistor to IOV_DD on the CS pin. Refer to the Power-On Reset Sequencing section for further details.
Stand-Alone Operation
The serial clock can be a continuous or a gated clock. The first falling edge of CS starts the operation cycle.
Exactly 24 falling clock edges must be applied before CS is brought back high again. If CS is brought high before
the 24th falling SCLK edge, then the data written are not transferred into the internal registers. If more than 24
falling SCLK edges are applied before CS is brought high, then the last 24 bits are used. The device internal
registers are updated from the Shift Register on the rising edge of CS. In order for another serial transfer to take
place, CS must be brought low again.
When the data have been transferred into the chosen register of the addressed DAC, all DAC latches and analog
outputs can be updated by taking LDAC low.
Daisy-Chain Operation
For systems that contain more than one device, the SDO pin can be used to daisy-chain multiple devices
together. Daisy-chain operation can be useful in system diagnostics and in reducing the number of serial
interface lines. Note that before daisy-chain operation can begin, the SDO pin must be enabled by setting the
SDO disable bit (DSDO) in the Configuration Register to '0'; this bit is cleared by default.
The DAC8718 provides two modes for daisy-chain operation: normal and sleep. The SLEEP bit in the SPI Mode
register determines which mode is used.
In Normal mode (SLEEP bit = '0'), the data clocked into the SDI pin are transferred into the Shift Register. The
first falling edge of CS starts the operating cycle. SCLK is continuously applied to the SPI Shift Register when CS
is low. If more than 24 clock pulses are applied, the data ripple out of the Shift Register and appear on the SDO
line. These data are clocked out on the rising edge of SCLK and are valid on the falling edge. By connecting the
SDO pin of the first device to the SDI input of the next device in the chain, a multiple-device interface is
constructed. Each device in the system requires 24 clock pulses. Therefore, the total number of clock cycles
must equal 24 × N, where N is the total number of DAC8718s in the chain. When the serial transfer to all devices
is complete, CS is taken high. This action latches the data from the SPI Shift Registers to the device internal
registers for each device in the daisy-chain, and prevents any further data from being clocked in. The serial clock
can be a continuous or a gated clock. Note that a continuous SCLK source can only be used if CS is held low for
the correct number of clock cycles. For gated clock mode, a burst clock containing the exact number of clock
cycles must be used and CS must be taken high after the final clock in order to latch the data.
In Sleep mode (SLEEP bit = '1'), the data clocked into SDI are routed to the SDO pin directly; the Shift Register
is bypassed. The first falling edge of CS starts the operating cycle. When SCLK is continuously applied with CS
low, the data clocked into the SDI pin appear on the SDO pin almost immediately (with approximately a 5 ns
delay; see the Timing Diagrams section); there is no 24 clock delay, as there is in normal operting mode. While
in Sleep mode, no data bits are clocked into the Shift Register, and the device does not receive any new data or
commands. Putting the device into Sleep mode eliminates the 24 clock delay from SDI to SDO caused by the
Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): DAC8718
Submit Documentation Feedback
45