DAC8718 Datasheet, PDF (43/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
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SBAS467A – MAY 2009 – REVISED DECEMBER 2009
UPDATING THE DAC OUTPUTS
Depending on the status of both CS and LDAC, and after data have been transferred into the DAC Data
registers, the DAC outputs can be updated either in asynchronous mode or synchronous mode. This update
mode is established at power-on. If asynchronous mode is desired, the LDAC pin must be permanently tied low
before power is applied to the device. If synchronous mode is desired, LDAC must be logic high before and
during power-on.
The DAC8718 updates a DAC latch only if it has been accessed since the last time LDAC was brought low or if
the LD bit is set to '1', thereby eliminating any unnecessary glitch. Any DAC channels that were not accessed are
not loaded again. When the DAC latch is updated, the corresponding output changes to the new level
immediately.
Asynchronous Mode
In this mode, the LDAC pin is set low at power-up. This action places the DAC8718 into Asynchronous mode,
and the LD bit and LDAC signal are ignored. When the correction engine is off (SCE bit = '0'), the DAC Data
Registers and DAC latches are updated immediately when CS goes high. When the correction engine is on (SCE
bit = '1'), each DAC latch is updated individually when the correction engine updates the corresponding DAC
Data Register.
Synchronous Mode
To use this mode, set LDAC high before CS goes low, and then take LDAC low or set the LD bit to '1' after CS
goes high. If LDAC goes low or if the LD bit is set to '1' when SCE = '0', all DAC latches are updated
simultaneously. If LDAC goes low or if the LD bit is set to '1' when SCE = '1', all DAC latches are updated
simultaneously after the correction engine has updated the corresponding DAC register.
In this mode, when LDAC stays high, the DAC latch is not updated; therefore, the DAC output does not change.
The DAC latch is updated by taking LDAC low (or by setting the LD bit in the Configuration Register to '1') any
time after the delay of t₉ from the rising edge of CS. If the timing requirement of t₉ is not satisfied, invalid data are
loaded. Refer to the Timing Diagrams and the Configuration Register (Table 11) for details.
Copyright © 2009, Texas Instruments Incorporated
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