DAC8718 Datasheet, PDF (41/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
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SBAS467A – MAY 2009 – REVISED DECEMBER 2009
GENERAL-PURPOSE INPUT/OUTPUT PINS (GPIO-0 to GPIO-2)
The GPIO pins are general-purpose, bidirectional, digital input/outputs, as shown in Figure 99. When a GPIO pin
acts as an output, the pin status is determined by the corresponding GPIO bit in the GPIO Register. The pin
output is high-impedance when the GPIO bit is set to '1', and is logic low when the GPIO bit is cleared to '0'.
Note that a pull-up resistor to IOV_DD is required when using a GPIO pin as an output. When a GPIO pin acts as
an input, the digital value on the pin is acquired by reading the corresponding GPIO bit. After power-on reset, or
any forced hardware or software reset, the GPIO bits are set to '1', and the GPIO pins are in a high-impedance
state. If not used, the GPIO pins must be tied to either DGND or to IOV_DD through a pull-up resistor. Leaving the
GPIO pins floating can cause high IOV_DD supply currents.
+V
Bit GPIO-n (when writing)
GPIO-n
Enable
Bit GPIO-n (when reading)
Figure 99. GPIO-n Pin
ANALOG OUTPUT PIN (CLR)
The CLR pin is an active low input that should be high for normal operation. When this pin is in logic '0', all V_OUT
outputs connect to AGND-x through internal 15kΩ resistors and are cleared to 0V, and the output buffer is in a
Hi-Z state. While CLR is low, all LDAC pulses are ignored. When CLR is taken high again while the LDAC is
high, the DAC outputs remain cleared until LDAC is taken low. However, if LDAC is tied low, taking CLR back to
high sets the DAC output to the level defined by the value of the DAC latch. The contents of the Zero Registers,
Gain Registers, Input Data Registers, DAC Data Registers, and DAC latches are not affected by taking CLR low.
Copyright © 2009, Texas Instruments Incorporated
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