DAC8718 Datasheet, PDF (48/60 Pages) Texas Instruments – Octal, 16-Bit, Low-Power, High-Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER

DAC8718
SBAS467A – MAY 2009 – REVISED DECEMBER 2009
www.ti.com
Table 10. Register Map
ADDRESS BITS
DATA BITS
A4 A3 A2 A1 A0 D15
D14
D13 D12 D11 D10 D9 D8
D7
D6
D5 D4 D3:D0
REGISTER
0 0 0 0 0 A/B
LD
RST PD-A PD-B SCE X GAIN-A GAIN-B DSDO NOP W2
00001
0 0 0 1 0 GPIO-2 GPIO-1 GPIO-0
Analog Monitor Select
X ⁽¹⁾
X ⁽¹⁾
Configuration
Register
X⁽¹⁾ Monitor Register
GPIO Register
00011
OS15:OS0 ⁽²⁾
Offset DAC-A
Data
00100
OS15:OS0 ⁽²⁾
Offset DAC-B
Data
00101
0 0 1 1 0 SLEEP
Reserved ⁽³⁾
Reserved ⁽³⁾
Reserved
SPI MODE
00111
DB15:DB0
Broadcast
01000
DB15:DB0
DAC-0
01001
DB15:DB0
DAC-1
01010
DB15:DB0
DAC-2
01011
DB15:DB0
DAC-3
01100
DB15:DB0
DAC-4
01101
DB15:DB0
DAC-5
01110
DB15:DB0
DAC-6
01111
DB15:DB0
DAC-7
10000
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-0
11000
G15:G0, default = 32768 (8000h), straight binary
Gain Register-0
10001
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-1
11001
G15:G0, default = 32768 (8000h), straight binary
Gain Register-1
10010
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-2
11010
G15:G0, default = 32768 (8000h), straight binary
Gain Register-2
10011
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-3
11011
G15:G0, default = 32768 (8000h), straight binary
Gain Register-3
10100
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-4
11100
G15:G0, default = 32768 (8000h), straight binary
Gain Register-4
10101
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-5
11101
G15:G0, default = 32768 (8000h), straight binary
Gain Register-5
10110
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-6
11110
G15:G0, default = 32768 (8000h), straight binary
Gain Register-6
10111
Z15:Z0, default = 0 (0000h), twos complement
Zero Register-7
11111
G15:G0, default = 32768 (8000h), straight binary
Gain Register-7
(1) X = don't care—writing to this bit has no effect; reading the bit returns '0'.
(2) Table 7 lists the default values for a dual power supply. Offset DAC A and Offset DAC B are trimmed in manufacturing to minimize the
error for symmetrical output. The default value may vary no more than ±10 LSB from the nominal number listed in Table 7. For a single
power supply, the Offset DACs are turned off.
(3) Writing to a reserved bit has no effect; reading the bit returns '0'.
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