DRV8701_15 Datasheet, PDF (33/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

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10 Layout
DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
10.1 Layout Guidelines
Bypass the VM pin to GND using a low-ESR ceramic bypass capacitor with a recommended value of 0.1 µF
rated for VM. Place this capacitor as close to the VM pin as possible with a thick trace or ground plane
connection to the device GND pin.
Bypass the VM pin to ground using a bulk capacitor rated for VM. This component may be an electrolytic. This
capacitance must be at least 10 µF. The bulk capacitor should be placed to minimize the distance of the high-
current path through the external FETs. The connecting metal trace widths should be as wide as possible, and
numerous vias should be used when connecting PCB layers. These practices minimize inductance and allow the
bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor in between the CPL and CPH pins. The value for this component is 0.1 µF
rated for VM. Place this component as close to the pins as possible.
Place a low-ESR ceramic capacitor in between the VM and VCP pins. The value for this component is 1 µF rated
for 16 V. Place this component as close to the pins as possible.
Bypass AVDD and DVDD to ground with ceramic capacitors rated at 6.3 V. Place these bypassing capacitors as
close to the pins as possible.
If desired, align the external NMOS FETs as shown in Figure 42 to facilitate layout. Route the SH2 and SH1 nets
to the motor.
Use separate traces to connect the SP and SN pins to the R_SENSE terminals.
10.2 Layout Example
GND
1 µF
1 µF
AVDD ⁷
DVDD 8
nFAULT 9
SNSOUT 10
SO 11
R_IDRIVE
IDRIVE 12
0.1 µF 1 µF
0.1 µF
GND
(PPAD)
24 _GH2
23 SH2
22 _GL2
21 _SP
20 _SN
19 GL1
+
10 µF
minimum
D
D
D
D
S
S
S
G
R_SENSE
S
S
S
G
GND
G
S
S
S
D
D
D
D
D
D
D
D
GND
Figure 42. Layout Recommendation
D
G
D
S
D
S
D
S
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