DRV8701_15 Datasheet, PDF (22/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
www.ti.com
7.3.10 Charge Pump
A charge pump is integrated to supply a high-side NMOS gate drive voltage of V_HGS. The charge pump requires
a capacitor between the VM and VCP pins. Additionally a low-ESR ceramic capacitor is required between pins
CPH and CPL. When VM is below 12 V, this charge pump behaves as a doubler and generates VCP = 2 × VM –
1.5 V if unloaded. Above VM = 12 V, the charge pump regulates VCP such that VCP = VM + 9.5 V.
1 µF
VM
VCP
0.1 µF
CPH
CPL
Charge
VM
Pump
Figure 29. Charge Pump Diagram
7.3.11 LDO Voltage Regulators
Two LDO regulators are integrated into the DRV8701. They can be used to provide the supply voltage for a low-
power microcontroller or other low-current devices. For proper operation, bypass the AVDD and DVDD pins to
GND using ceramic capacitors.
The AVDD output voltage is nominally 4.8 V, and the DVDD output is nominally 3.3 V. When the AVDD or DVDD
current load exceeds 30 mA, the LDO behaves like a constant current source. The output voltage drops
significantly with currents greater than this limit.
Note that AVDD and DVDD are disabled when the device is in sleep mode (nSLEEP = 0). In addition, when an
overtemperature (TSD) or undervoltage (UVLO) fault is encountered, the AVDD regulator is shut off.
VM
+
-
VM
+
-
AVDD
DVDD
4.8 V
30 mA
1 µF max
3.3 V
30 mA
1 µF max
Figure 30. AVDD and DVDD LDOs
The power dissipated in the DRV8701 due to these LDOs may be approximated by:
Power = (VM – AVDD) × I_AVDD + (VM – DVDD) × I_DVDD
(3)
For example at VM = 24 V, drawing 10 mA out of both AVDD and DVDD results in a power dissipation of:
Power = (24 V – 4.8 V) × 10 mA + (24 V – 3.3 V) × 10 mA = 192 mW + 207 mW = 399 mW
(4)
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