DRV8701_15 Datasheet, PDF (24/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
www.ti.com
7.3.13 Protection Circuits
The DRV8701 is fully protected against VM undervoltage, charge pump undervoltage, overcurrent, gate driver
shorts, and overtemperature events.
7.3.13.1 VM Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the UVLO threshold voltage, all FETs in the H-bridge are
disabled, the charge pump is disabled, AVDD is disabled, and the nFAULT pin is driven low. Operation resumes
when VM rises above the UVLO threshold. The nFAULT pin is released after operation has resumed.
7.3.13.2 VCP Undervoltage Lockout (CPUV)
If at any time the voltage on the VCP pin falls below the charge pump undervoltage threshold voltage (V_CPUV), all
FETs in the H-bridge are disabled and the nFAULT pin is driven low. Operation resumes when VCP rises above
the CPUV threshold. The nFAULT pin is released after operation has resumed.
7.3.13.3 Overcurrent Protection (OCP)
Overcurrent is sensed by monitoring the V_DS voltage drop across the external FETs (see Figure 28). If the
voltage across a driven FET exceeds the overcurrent trip threshold (V_{DS OCP}) for longer than the OCP deglitch
time (t_OCP), an OCP event is recognized. As a result, all FETs in the H-bridge are disabled and the nFAULT pin is
driven low; the driver is re-enabled after the OCP retry period (t_RETRY) has passed. nFAULT releases high-Z
again at after the retry time. If the fault condition is still present, the cycle repeats. If the fault is no longer present,
normal operation resumes and nFAULT remains released high-Z.
This V_DS overcurrent monitor on the high-side FETs can be disabled by using a specific IDRIVE setting. This
allows the system to have a higher DRV8701 VM supply than the H-bridge supply.
In addition to this FET V_DS monitor, an overcurrent condition is also detected if the voltage at SP exceeds
V_{SP OCP}.
7.3.13.4 Pre-Driver Fault (PDF)
The GHx and GLx pins are monitored such that if the voltage on the external FET gate does not increase above
1 V (when sourcing current) or decrease below 1 V (when sinking current) after t_DRIVE, a pre-driver fault is
detected. The device encounters this fault if GHx or GLx are shorted to GND, SHx, or VM. Additionally, the
device encounters the pre-driver fault if the IDRIVE setting selected is not sufficient to turn on the external FET.
As a result, all FETs in the H-bridge are disabled and the nFAULT pin is driven low. The driver is re-enabled after
the retry period (t_RETRY) has passed. The nFAULT pin is released after operation has resumed.
7.3.13.5 Thermal Shutdown (TSD)
If the die temperature exceeds T_TSD, all FETs in the H-bridge are disabled, the charge pump is shut down, AVDD
is disabled, and the nFAULT pin is driven low. After the die temperature has fallen below T_TSD – T_HYS, operation
automatically resumes. The nFAULT pin is released after operation has resumed.
Fault
VM undervoltage
(UVLO)
VCP undervoltage
(CPUV)
External FET overload
(OCP)
Pre-driver fault (PDF)
Thermal shutdown
(TSD)
Condition
VM ≤ V_UVLO
VCP < V_CPUV
V_DS ≥ 1.0 V or
V_SP – V_SN > 1.0 V
Gate voltage
unchanged after t_DRIVE
T_J ≥ 150°C
Table 7. Fault Response
H-Bridge Charge Pump
Disabled
Disabled
AVDD
Disabled
Disabled
Operating
Operating
Disabled
Operating
Operating
Disabled
Operating
Operating
Disabled
Disabled
Disabled
DVDD
Operating
Operating
Operating
Operating
Operating
Recovery
VM ≥ V_UVLO
VCP > V_CPUV
t_RETRY
t_RETRY
T_J ≤ 130°C
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