DRV8701_15 Datasheet, PDF (20/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
www.ti.com
7.3.6 IDRIVE Pin
The rise and fall times of the H-bridge output (SHx pins) can be adjusted by setting the IDRIVE resistor value or
forcing a voltage onto the IDRIVE pin. The FET gate voltage ramps faster if a higher IDRIVE setting is chosen.
The FET gate ramp directly affects the H-bridge output rise and fall time.
Tying IDRIVE to GND selects the lowest drive setting of 6-mA source and 12.5-mA sink. If this pin is left
unconnected, then the 100-mA source and 200-mA sink setting are selected.
If IDRIVE is shorted to AVDD, then the VDS OCP monitor on the high-side FETs is disabled. In this setting, the
gate driver is configured as 25-mA source and 50-mA sink.
IDRIVE
AVDD
190kŸ
310kŸ
+
4.3V -
+
3.7V -
+
2.5V -
+
1.3V -
+
0.1V -
Digital
Core
Figure 27. IDRIVE Pin Internal Circuitry
IDRIVE Resistance
<1 kΩ to GND
33 kΩ ±5% to GND
200 kΩ ±5% to GND
>500 kΩ to GND, High-Z
68 kΩ ±5% to AVDD
<1 kΩ to AVDD
Table 5. IDRIVE Pin Configuration Settings
IDRIVE Voltage
GND
0.7 V ±5%
2 V ±5%
3 V ±5%
4 V ±5%
AVDD
Source Current
(I_DRIVE,SRC)
6 mA
12.5 mA
25 mA
100 mA
150 mA
25 mA
Sink Current (I_DRIVE,SNK)
12.5 mA
25 mA
50 mA
200 mA
300 mA
50 mA
HS OCP Monitor
ON
ON
ON
ON
ON
OFF
<1 kΩ to GND
«««
IDRIVE
Table 6. IDRIVE Pin Resistor Settings
33 kΩ ±5% to GND
200 kΩ ±5% to GND
>500 kΩ to GND, High-Z
68 kΩ ±5% to AVDD
AVDD
<1 kΩ to AVDD
AVDD
IDRIVE
IDRIVE
R_IDRIVE
IDRIVE
IDRIVE
R_IDRIVE
«««
«««
IDRIVE
6 / 12.5 mA
IDRIVE
12.5 / 25 mA (33 kΩ)
25 / 50 mA (200 kΩ)
IDRIVE
100 / 200 mA
IDRIVE
150 / 300 mA
IDRIVE
25 / 50 mA
HS OCP monitor off
20
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