DRV8701_15 Datasheet, PDF (26/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
www.ti.com
7.4 Device Functional Modes
The DRV8701 is active unless the nSLEEP pin is brought low. In sleep mode, the charge pump is disabled, the
H-bridge FETs are High-Z, and the AVDD and DVDD regulators are disabled. Note that t_SLEEP must elapse after
a falling edge on the nSLEEP pin before the device is in sleep mode. The DRV8701 is brought out of sleep mode
if nSLEEP is brought high. Note that t_WAKE must elapse before the outputs change state after wake-up.
While nSLEEP is brought low, all external H-bridge FETs are disabled. The high-side gate pins GHx are pulled to
the output node SHx by an internal resistor, and the low-side gate pins GLx are pulled to GND.
When VM is not applied, and during the power-on time (t_ON), the outputs are disabled using weak pulldown
resistors between the GHx and SHx pins and between GLx and GND.
Unpowered
Sleep mode
Operating
Condition
VM < V_UVLO
V_UVLO < VM
nSLEEP low
V_UVLO < VM
nSLEEP high
Table 8. Functional Modes
Charge Pump
Disabled
GHx
GLx
AVDD and DVDD
Weak pulldown to SHx Weak pulldown to GND
Disabled
Disabled
Strong pulldown to GND Strong pulldown to GND
Disabled
Enabled
Depends on inputs
Depends on inputs
Operating
26
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