DRV8701_15 Datasheet, PDF (3/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

www.ti.com
5 Pin Configuration and Functions
RGE Package
24-Pin VQFN
DRV8701E Top View
VM 1
VCP 2
CPH 3
CPL 4
GND 5
VREF 6
GND
(PPAD)
18 SH1
17 GH1
16 GND
15 PH
14 EN
13 nSLEEP
DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
RGE Package
24-Pin VQFN
DRV8701P Top View
VM 1
VCP 2
CPH 3
CPL 4
GND 5
VREF 6
GND
(PPAD)
18 SH1
17 GH1
16 GND
15 IN1
14 IN2
13 nSLEEP
PIN
NAME
NO.
EN
14
PH
15
PIN
NAME
NO.
IN1
15
IN2
14
PIN
NAME
NO.
VM
1
GND
VCP
CPH
CPL
DVDD
5
16
PPAD
2
3
4
8
AVDD
7
nSLEEP
13
IDRIVE
12
TYPE
Input
Input
DRV8701E (PH/EN)
DESCRIPTION
Bridge enable input
Bridge phase input
Logic low places the bridge in brake mode; see Table 1
Controls the direction of the H-bridge; see Table 1
TYPE
Input
Input
DRV8701P (PWM)
DESCRIPTION
Bridge PWM input
Logic controls the state of H-bridge; see Table 2
TYPE
Power Power supply
Common Pins
DESCRIPTION
Connect to motor supply voltage; bypass to GND with a 0.1-µF
ceramic plus a 10-µF minimum capacitor rated for VM; additional
capacitance may be required based on drive current
Power Device ground
Must be connected to ground
Power
Power
Power
Power
Input
Input
Charge pump output
Connect a 16-V, 1-µF ceramic capacitor to VM
Charge pump switching nodes
Connect a 0.1-µF X7R capacitor rated for VM between CPH and
CPL
Logic regulator
Analog regulator
Device sleep mode
Gate drive current setting pin
3.3-V logic supply regulator; bypass to GND with a 6.3-V, 1-µF
ceramic capacitor
4.8-V analog supply regulator; bypass to GND with a 6.3-V, 1-µF
ceramic capacitor
Pull logic low to put device into a low-power sleep mode with FETs
High-Z; internal pulldown
Resistor value or voltage forced on this pin sets the gate drive
current; see applications section for more details
Copyright © 2015, Texas Instruments Incorporated
Product Folder Links: DRV8701
Submit Documentation Feedback
3