DRV8701_15 Datasheet, PDF (12/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
7 Detailed Description
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7.1 Overview
The DRV8701 is an H-bridge gate driver (also called a pre-driver or controller). The device integrates FET gate
drivers in order to control four external NMOS FETs. The device can be powered with a supply voltage between
5.9 and 45 V.
A simple PH/EN (DRV8701E) or PWM (DRV8701P) interface allows interfacing to the controller circuit.
A low-power sleep mode is included, which can be enabled using the nSLEEP pin.
The gate drive strength can be adjusted to optimize a system for a given FET without adding external resistors in
series with the FET gates. The IDRIVE pin allows for selection of the peak current driven into the external FET
gate. Both the high-side and low-side FETs are driven with a V_GS of 9.5 V nominally when VM > 12 V. At lower
VM voltages, the V_GS is reduced. The high-side gate drive voltage is generated using a doubler-architecture
charge pump that regulates to VM + 9.5 V.
This device greatly reduces the component count of discrete motor driver systems by integrating the necessary
FET drive circuitry into a single device. In addition, the DRV8701 adds protection features above traditional
discrete implementations: UVLO, OCP, pre-driver faults, and thermal shutdown.
A start-up (inrush) or running current limitation is built in using a fixed time-off current chopping scheme. The
chopping current level is set by choosing the sense resistor value and by setting a voltage on the VREF pin.
A shunt amplifier output is provided for accurate current measurements by the system controller. The SO pin
outputs a voltage that is 20 times the voltage seen across the sense resistor.
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