DRV8701_15 Datasheet, PDF (19/42 Pages) Texas Instruments – DRV8701 Brushed DC Motor Full-Bridge Gate Driver

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DRV8701
SLVSCX5B – MARCH 2015 – REVISED JULY 2015
When changing the state of the output, the peak current (I_DRIVE) is applied for a short drive period (t_DRIVE) to
charge the gate capacitance. After this time, a weaker current source (I_HOLD) is used to keep the gate at the
desired state. When selecting the gate drive strength for a given external FET, the selected current must be high
enough to fully charge and discharge the gate during t_DRIVE, or excessive power will be dissipated in the FET.
During high-side turn-on, the low-side gate is pulled low with a strong pull-down (I_STRONG). This prevents the low-
side FET Q_GS from charging and keeps the FET off, even when there is fast switching at the outputs.
The pre-driver circuits include enforcement of a dead time in analog circuitry, which prevents the high-side and
low-side FETs from conducting at the same time. When switching FETs on, this handshaking prevents the high-
or low-side FET from turning on until the opposite FET has been turned off.
t_DRIVE
High-side
IHOLD
gate drive
current
IHOLD
IHOLD
High-side
V_GS
t_DRIVE
Low-side ^IHOLD
gate drive
current
IHOLD
IHOLD
Low-side
V_GS
Figure 25. Gate Driver Output to Control External FETs
Q_GD Miller charge
When a FET gate is turned on, three different capacitances must be charged.
• Q_GS – Gate-to-source charge
• Q_GD – Gate-to-drain charge (miller charge)
• Remaining Q_G
The FET output is slewing primarily during the Q_GD charge.
10
25
VM
D
8
20
VGHS
CGD
GHx G
6
15
Pre-Drive
CGS
SHx
4
10
S
2
5
10
20
30
40
50
Q_GS
Q_GD
Remaining Q_G
Q_G gate charge (nC)
Figure 26. Example FET Gate Charging Profile
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