W83977EG-AW Datasheet, PDF (66/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
Bit 4: Read/Write (Valid only in ECP Mode)
1
Disables the interrupt generated on the asserting edge of nFault.
0
Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted
(interrupt) an interrupt will be generated and this bit is written from a 1 to 0.
Bit 3: Read/Write
1
Enables DMA.
0
Disables DMA unconditionally.
Bit 2: Read/Write
1
Disables DMA and all of the service interrupts.
0
Enables one of the following cases of interrupts. When one of the service interrupts
has occurred, the serviceIntr bit is set to a 1 by hardware. This bit must be reset to
0 to re-enable the interrupts. Writing a 1 to this bit will not cause an interrupt.
(a) dmaEn = 1: During DMA this bit is set to a 1 when terminal count is reached.
(b) dmaEn = 0 direction = 0: This bit is set to 1 whenever there are writeIntr
Threshold or more bytes free in the FIFO.
(c) dmaEn = 0 direction = 1: This bit is set to 1 whenever there are readIntr
Threshold or more valid bytes to be read from the FIFO.
Bit 1: Read only
0
The FIFO has at least 1 free byte.
1
The FIFO cannot accept another byte or the FIFO is completely full.
Bit 0: Read only
0
The FIFO contains at least 1 byte of data.
1
The FIFO is completely empty.
7.3.11 Bit Map of ECP Port Registers
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
D7
D6
D5
PD7
PD6
PD5
Addr/RLE Address or RLE field
nBusy
nAck
PError
1
1
Directio
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
0
0
0
compress intrValue
1
MODE
Notes:
1. These registers are available in all modes.
2. All FIFOs use one common 16-byte FIFO.
D4
PD4
Select
ackIntEn
1
1
nErrIntrEn
D3
PD3
nFault
SelectIn
0
1
dmaEn
D2
D1
PD2
PD1
1
1
nInit
autofd
0
0
1
1
serviceIntr full
D0
PD0
1
strobe
0
1
empty
NOTE
2
1
1
2
2
2
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