W83977EG-AW Datasheet, PDF (52/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
Bit 0: This bit enables the 16550 (FIFO) mode of the UART. This bit should be set to a logical 1 before
other bits of UFR are programmed.
6.2.6 Interrupt Status Register (ISR) (Read only)
This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3
bits.
7 65 4 3 21 0
00
0 if interrupt pending
Interrupt Status bit 0
Interrupt Status bit 1
Interrupt Status bit 2
FIFOs enabled
FIFOs enabled
Bit 7, 6: These two bits are set to a logical 1 when UFR bit 0 = 1.
Bit 5, 4: These two bits are always logic 0.
Bit 3: In 16450 mode, this bit is 0. In 16550 mode, both bit 3 and 2 are set to a logical 1 when a time-
out interrupt is pending.
Bit 2, 1: These two bits identify the priority level of the pending interrupt, as shown in the table below.
Bit 0: This bit is a logical 1 if there is no interrupt pending. If one of the interrupt sources has occurred,
this bit will be set to a logical 0.
TABLE 6-4 INTERRUPT CONTROL FUNCTION
ISR
INTERRUPT SET AND FUNCTION
Bit Bit Bit Bit Interrupt ^{Interrupt Type}
3 2 1 0 priority
Interrupt Source
Clear Interrupt
0 001
-
-
No Interrupt pending
-
0 1 1 0 First
UART Receive
Status
1. OER = 1 2. PBER =1
3. NSER = 1 4. SBD = 1
Read USR
0 1 0 0 Second RBR Data Ready
1. RBR data ready
2. FIFO interrupt active level
reached
1. Read RBR
2. Read RBR until FIFO
data under active level
Data present in RX FIFO for 4
1 1 0 0 Second FIFO Data Timeout characters period of time since last Read RBR
access of RX FIFO.
0 0 1 0 Third
TBR Empty
TBR empty
1. Write data into TBR
2. Read ISR (if priority is
third)
0 0 0 0 Fourth Handshake status
1. TCTS = 1 2. TDSR = 1
3. FERI = 1 4. TDCD = 1
Read HSR
** Bit 3 of ISR is enabled when bit 0 of UFR is logical 1.
-50-