W83977EG-AW Datasheet, PDF (47/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
TABLE 6-1 UART Register Bit Map
BIT NUMBER
REGISTER ADDRESS
BASE
0
1
2
3
4
5
6
7
+0
BDLAB =
0
+0
BDLAB =
0
+1
BDLAB =
0
+2
Receiver
Buffer
Register
(Read Only)
Transmitter
Buffer
Register
(Write Only)
Interrupt
Control
Register
Interrupt
Status
Register
(Read Only)
RBR
TBR
ICR
ISR
RX Data RX Data
Bit 0
Bit 1
TX Data TX Data
Bit 0
Bit 1
RBR Data
Ready
Interrupt
Enable
(ERDRI)
TBR
Empty
Interrupt
Enable
(ETBREI)
"0" if
Interrupt
Pending
Interrupt
Status
Bit (0)
RX Data
Bit 2
TX Data
Bit 2
USR
Interrupt
Enable
(EUSRI)
Interrupt
Status
Bit (1)
+2
UART FIFO
Control
Register
(Write Only)
UFR
FIFO
Enable
RCVR
FIFO
Reset
XMIT
FIFO
Reset
Data
Data
Multiple
UART
Length Length _{Stop Bits}
+3
Control UCR Select Select _Enable
Register
Bit 0
Bit 1
(DLS0) (DLS1) ^(MSBE)
+4
Handshake
Control
Register
HCR
Data
Terminal
Ready
(DTR)
Request
to
Send
(RTS)
Loopback
RI
Input
RBR Data Overrun Parity Bit
+5
UART Status
Register
USR
Ready
Error
Error
(RDR) (OER) (PBER)
Handshake
CTS
DSR RI Falling
+6
Status HSR ^{Toggling Toggling Edge}
Register
(TCTS) (TDSR) (FERI)
+7
User Defined
Register
UDR
+0
Baudrate
BDLAB = ^{Divisor Latch BLL}
1
Low
+1
Baudrate
BDLAB = ^{Divisor Latch BHL}
1
High
Bit 0
Bit 0
Bit 8
Bit 1
Bit 1
Bit 2
Bit 2
Bit 9
Bit 10
RX Data
Bit 3
TX Data
Bit 3
HSR
Interrupt
Enable
(EHSRI)
Interrupt
Status
Bit (2)**
DMA
Mode
Select
Parity
Bit
Enable
(PBE)
IRQ
Enable
No Stop
Bit
Error
(NSER)
DCD
Toggling
(TDCD)
Bit 3
Bit 3
Bit 11
RX Data RX Data
Bit 4
Bit 5
TX Data TX Data
Bit 4
Bit 5
0
0
0
0
Reserved Reversed
Even
Parity
Enable
(EPE)
Parity
Bit Fixed
Enable
PBFE)
Internal
Loopback
0
Enable
Silent
Byte
Detected
(SBD)
TBR
Empty
(TBRE)
Clear
to Send
(CTS)
Data Set
Ready
(DSR)
Bit 4
Bit 5
Bit 4
Bit 5
Bit 12
Bit 13
RX Data RX Data
Bit 6
Bit 7
TX Data TX Data
Bit 6
Bit 7
0
0
FIFOs
Enabled
**
FIFOs
Enabled
**
RX
Interrupt
Active
Level
(LSB)
RX
Interrupt
Active
Level
(MSB)
Set
Silence
Enable
(SSE)
Baudrate
Divisor
Latch
Access Bit
(BDLAB)
0
0
TSR
Empty
(TSRE)
Ring
Indicator
(RI)
RX FIFO
Error
Indication
(RFEI) **
Data
Carrier
Detect
(DCD)
Bit 6
Bit 7
Bit 6
Bit 7
Bit 14
Bit 15
*: Bit 0 is the least significant bit. The least significant bit is the first bit serially transmitted or received.
**: These bits are always 0 in 16450 Mode.
Publication Release Date: Apr. 2006
-45-
Revision 1.2