W83977EG-AW Datasheet, PDF (112/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
Bit 3: PRTIRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to printer port's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to printer port's IRQ.
Bit 2: FDCIRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to FDC's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to FDC's IRQ.
Bit 1: URAIRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to UART A's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to UART A's IRQ.
Bit 0: URBIRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to UART B's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to UART B's IRQ.
CRF7 (Default 0x00)
Bit 7 - 5: Reserved. Return zero when read.
Bit 3: Reserved. Return zero when read.
Bit 4 and Bit 2 - 0:Enable bits of the SMI#/SCI# generation due to the individual GPIO IRQ
functions.
Bit 4: WDTIRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to watch dog timer's IRQ.
Bit 2: COMIRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to common IRQ function's IRQ.
Bit 1: GP11IRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to GP11 interrupt steering's IRQ.
Bit 0: GP10IRQEN.
= 0 disable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's IRQ.
= 1 enable the generation of an SMI#/SCI# interrupt due to GP10 interrupt steering's IRQ.
CRF9 (Default 0x00)
Bit 7 - 3: Reserved. Return zero when read.
Bit 2: SCI_EN: Select the power management events to be either an SCI# OR SMII# interrupt for
the IRQ events. Note that: this bit is valid only when SMISCI_OE = 1.
= 0 the power management events will generate an SMI# event.
= 1 the power management events will generate an SCI# event.
Bit 1: FSLEEP: This bit selects the fast expiry time of individual devices
= 0 1 second.
= 1 8 milli-seconds.
Bit 0: SMISCI_OE: This is the SMI# and SCI# enable bit.
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