W83977EG-AW Datasheet, PDF(11/142 Page) Nuvotem Talema – These products are not designed for use in life support appliances

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W83977EG-AW Datasheet, PDF (11/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

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W83977EF-AW/W83977EG-AW

4. PIN DESCRIPTION

Note: Please refer to Section 11.2 DC CHARACTERISTICS for details.

I/O6t - TTL level bi-directional pin with 6 mA source-sink capability

I/O8t - TTL level bi-directional pin with 8 mA source-sink capability

I/O8

- CMOS level bi-directional pin with 8 mA source-sink capability

I/O12t - TTL level bi-directional pin with 12 mA source-sink capability

I/O12 - CMOS level bi-directional pin with 12 mA source-sink capability

I/O16u - CMOS level bi-directional pin with 16 mA source-sink capability with internal pull-up resistor

I/OD16u - CMOS level bi-directional pin open drain output with 16 mA sink capability with internal pull-up resistor

I/O24t - TTL level bi-directional pin with 24 mA source-sink capability

OUT8t - TTL level output pin with 8 mA source-sink capability

OUT12t - TTL level output pin with 12 mA source-sink capability

OD12 - Open-drain output pin with 12 mA sink capability

OD24 - Open-drain output pin with 24 mA sink capability

INt

- TTL level input pin

INc

INcu

INcs

INts

INtsu

- CMOS level input pin

- CMOS level input pin with internal pull-up resitor

- CMOS level Schmitt-triggered input pin

- TTL level Schmitt-triggered input pin

- TTL level Schmitt-triggered input pin with internal pull-up resistor

4.1 Host Interface

SYMBOL

A0âA10

A11-A14

A15

D0âD5

D6âD7

IOR#

IOW#

AEN

74-84

86-89

109-114

116-117

105

106

107

IOCHRDY

108

118

DACK0#

119

GP16

(WDTO)

P15

I/O

INt

I/O12t

INts

OD24

INts

INtsu

I/O12t

FUNCTION

System address bus bits 0-10

System address bus bits 11-14

System address bus bit 15

System data bus bits 0-5

System data bus bits 6-7

CPU I/O read signal

CPU I/O write signal

System address bus enable

In EPP Mode, this pin is the IO Channel Ready output to

extend the host read/write cycle.

Master Reset; Active high; MR is low during normal

operations.

DMA Channel 0 Acknowledge signal. (CR2C bit 5_4 = 00,

default)

General purpose I/O port 1bit 6. (CR2C bit 5_4 = 01)

Alternate function from GP16: Watch dog timer output

KBC P15 I/O port. (CR2C bit 5_4 = 10)

Publication Release Date: Apr. 2006

-9-

Revision 1.2

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