W83977EG-AW Datasheet, PDF (51/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
Bit 6: This bit is the opposite of the RI # input. This bit is equivalent to bit 2 of HCR in loopback
mode.
Bit 5: This bit is the opposite of the DSR# input. This bit is equivalent to bit 0 of HCR in loopback
mode.
Bit 4: This bit is the opposite of the CTS# input. This bit is equivalent to bit 1 of HCR in loopback
mode.
Bit 3: TDCD. This bit indicates that the DCD# pin has changed state after HSR was read by the CPU.
Bit 2: FERI. This bit indicates that the RI # pin has changed from low to high state after HSR was
read by the CPU.
Bit 1: TDSR. This bit indicates that the DSR# pin has changed state after HSR was read by the CPU.
Bit 0: TCTS. This bit indicates that the CTS# pin has changed state after HSR was read.
6.2.5 UART FIFO Control Register (UFR) (Write only)
This register is used to control the FIFO functions of the UART.
7 6 54 3 210
FIFO enable
Receiver FIFO reset
Transmitter FIFO reset
DMA mode select
Reserved
Reserved
RX interrupt active level (LSB)
RX interrupt active level (MSB)
Bit 6, 7: These two bits are used to set the active level for the receiver FIFO interrupt. For example, if
the interrupt active level is set as 4 bytes, once there are more than 4 data characters in the
receiver FIFO, the interrupt will be activated to notify the CPU to read the data from the FIFO.
BIT 7
0
0
1
1
BIT 6
0
1
0
1
TABLE 6-3 FIFO TRIGGER LEVEL
RX FIFO INTERRUPT ACTIVE LEVEL (BYTES)
01
04
08
14
Bit 4, 5: Reserved
Bit 3: When this bit is programmed to logic 1, the DMA mode will change from mode 0 to mode 1 if
UFR bit 0 = 1.
Bit 2: Setting this bit to a logical 1 resets the TX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Bit 1: Setting this bit to a logical 1 resets the RX FIFO counter logic to initial state. This bit will clear to
a logical 0 by itself after being set to a logical 1.
Publication Release Date: Apr. 2006
-49-
Revision 1.2