W83977EG-AW Datasheet, PDF (59/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
These four registers are available only in EPP mode. Bit definitions of each data port are as follows:
76 5 4 3 2 1 0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
When accesses are made to any EPP data port, the contents of DB0-DB7 are buffered (non-inverting)
and output to the ports PD0-PD7 during a write operation. The leading edge of IOW# causes an EPP
data write cycle to be performed, and the trailing edge of IOW# latches the data for the duration of the
EPP write cycle.
During a read operation, ports PD0-PD7 are read, and the leading edge of IOR# causes an EPP read
cycle to be performed and the data to be output to the host CPU.
7.2.6 Bit Map of Parallel Port and EPP Registers
REGISTER
Data Port (R/W)
Status Buffer (Read)
Control Swapper (Read)
Control Latch (Write)
EPP Address Port R/W)
EPP Data Port 0 (R/W)
EPP Data Port 1 (R/W)
EPP Data Port 2 (R/W)
EPP Data Port 3 (R/W)
7
PD7
BUSY#
1
1
PD7
PD7
PD7
PD7
PD7
6
PD6
ACK#
1
1
PD6
PD6
PD6
PD6
PD6
5
PD5
PE
1
DIR
PD5
PD5
PD5
PD5
PD5
4
PD4
SLCT
IRQEN
IRQ
PD4
PD4
PD4
PD4
PD4
3
PD3
ERROR#
SLIN
SLIN
PD3
PD3
PD3
PD3
PD3
2
PD2
1
INIT#
INIT#
PD2
PD2
PD2
PD2
PD2
1
PD1
1
AUTOFD#
AUTOFD#
PD1
PD1
PD1
PD1
PD1
0
PD0
TMOUT
STROBE#
STROBE#
PD0
PD0
PD0
PD0
PD0
Publication Release Date: Apr. 2006
-57-
Revision 1.2