W83977EG-AW Datasheet, PDF (110/142 Pages) Nuvotem Talema – These products are not designed for use in life support appliances

W83977EF-AW/W83977EG-AW
CRF1 (Default 0x00)
Bit 7: WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume
event occurs. Upon setting this bit, the sleeping/working state machine will transition the
system to the working state. This bit is only set by hardware and is cleared by writing a 1 to
this bit position or by the sleeping/working state machine automatically when the global
standby timer expires.
= 0 the chip is in the sleeping state.
= 1 the chip is in the working state.
Bit 6: Device's trap status.
Bit 5 - 4: Reserved. Return zero when read.
Bit 3 - 0: Devices' trap status.
These bits of trap status indicate that the individual device Wakes-Up due to any I/O access,
IRQ, and external input to the device. The device's idle timer reloads the preset expiry
depending on which device wakes up. These 5 bits are controlled by the UART C, printer port,
FDC, UART A and UART B power down machines respectively . Writing a 1 clears this bit
and writing a 0 has no effect. Note that: the user is not supposed to change the status while
power management function is enabled.
Bit 6: URCTRAPSTS. UART C trap status.
= 0 UART C is now in the sleeping state.
= 1 UART C is now in the working state due to any UART C access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, and any transition on MODEM control input lines.
Bit 3: PRTTRAPSTS. Printer port trap status.
= 0 the printer port is now in the sleeping state.
= 1 the printer port is now in the workinging state due to any printer port access, any IRQ,
any DMA acknowledge, and any transition on BUSY, ACK#, PE, SLCT, and ERR#
pins.
Bit 2: FDCTRAPSTS. FDC trap status.
= 0 FDC is now in the sleeping state.
= 1 FDC is now in the working state due to any FDC access, any IRQ, any DMA
acknowledge, and any enabling of the motor enable bits in the DOR register.
Bit 1: URATRAPSTS. UART A trap status.
= 0 UART A is now in the sleeping state.
= 1 UART A is now in the working state due to any UART A access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, and any transition on MODEM control input lines.
Bit 0: URBTRAPSTS. UART B trap status.
= 0 UART B is now in the sleeping state.
= 1 UART B is now in the workinging state due to any UART B access, any IRQ, the
receiver begins receiving a start bit, the transmitter shift register begins transmitting a
start bit, and any transition on MODEM control input lines.
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