SM59R16A2 Datasheet, PDF (54/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: SPIC2
Address: F2h
7
6
5
4
3
2
1
0
Reset
SPIFD
TBC[2:0]
-
RBC[2:0]
00h
SPIFD: Full-duplex mode enable.
“1” : enable full-duplex mode.
“0” : disable full-duplex mode.
When it is set, the TBC[2:0] and RBC[2:0] will be reset and keep to zero, i.e., only 8-bit
communication is allowed in the full-duplex mode. When the master device transmits data to the
slave device via the MOSI line, the slave device responds sends data back to the master device
via the MISO line. This implies that full-duplex transmission with both out-data and in-data are
synchronized with the same clock SCK as shown below.
Input Shift register
SPIRXD
MISO
MISO
Output Shift register
SPITXD
Output Shift register
SPITXD
MOSI
MOSI
Input Shift register
SPIRXD
Clock Generator
SCK
SyncMos Master
SCK
SyncMos Slave
TBC[2:0]: SPI transmitter bit counter, here 1-8 bits are allowed except for the full-duplex mode
TBC[2:0] Bit counter
0:0:0
8 bits output
0:0:1
1 bit output
0:1:0
2 bits output
0:1:1
3 bits output
1:0:0
4 bits output
1:0:1
5 bits output
1:1:0
6 bits output
1:1:1
7 bits output
RBC[2:0]: SPI receiver bit counter, here 1-8 bits are allowed except for the full-duplex mode
RBC[2:0] Bit counter
0:0:0
8 bits input
0:0:1
1 bit input
0:1:0
2 bits input
0:1:1
3 bits input
1:0:0
4 bits input
1:0:1
5 bits input
1:1:0
6 bits input
1:1:1
7 bits input
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
54
Ver.B SM59R16A2/SM59R08A2 06/2009