SM59R16A2 Datasheet, PDF (51/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: IICA2
Address: FBh
7
6
5
4
3
2
1
0
Reset
IICA2[7:1]
Match2 or RW2 60h
R/W
R or R/W
Slave mode:
IICA2[7:1]: IIC Address registers
This is the second 7-bit address for this slave module.
It will be checked when an address (from master) is received
Match2: When IICA2 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus is stopped, this bit will clear automatically.
Master mode:
IICA2[7:1]: IIC Address registers
This 7-bit address indicate the slave with which it want to communicate.
RW2: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It is
used to tell the salve the direction of the following communication. If it is 1, the module is in
master receive mode. If 0, the module is in master transmit mode.
Mnemonic: IICRWD
7
6
5
4
3
2
IICRWD[7:0]
Address: FCh
1
0
Reset
00h
IICRWD[7:0]: IIC read write data buffer.
In receiving (read) mode, the received byte is stored here.
In transmitting mode, the byte to be shifted out through SDA stays here.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
51
Ver.B SM59R16A2/SM59R08A2 06/2009