SM59R16A2 Datasheet, PDF (53/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Mnemonic: SPIC1
Address: F1h
7
6
5
4
3
210
SPIEN SPIMSS SPISSP SPICKP SPICKE SPIBR[2:0]
Reset
08h
SPIEN: Enable SPI module. “1” is Enable. “0” is Disable.
SPIMSS: Master or Slave mode Select
“1” is Master mode.
“0” is Slave mode.
SPISSP: Slave Select (SS) active polarity (slave mode used only)
“1” - high active.
“0” - low active.
SPICKP: Clock idle polarity (master mode used only)
“1” – SCK high during idle. Ex :
“0” - SCK low during idle. Ex :
SPICKE: Clock sample edge select.
“1” – data latch in rising edge
“0” – data latch in falling edge.
* To ensure the data latch stability, SM59R16A2/SM59R08A2 generate the output data as given in
the following example, the other side can latch the stable data no matter in rising or falling edge.
sufficient set-up time sufficient hold time
SPIBR[2:0]: SPI baud rate select (master mode used only), here Fosc is the external crystal or oscillator
frequency :
SPIBR[2:0] Baud rate
0:0:0 Fosc/4
0:0:1 Fosc/8
0:1:0 Fosc/16
0:1:1 Fosc/32
1:0:0 Fosc/64
1:0:1 Fosc/128
1:1:0 Fosc/256
1:1:1 Fosc/512
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
53
Ver.B SM59R16A2/SM59R08A2 06/2009