SM59R16A2 Datasheet, PDF (39/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
10 Watchdog timer
The watchdog timer is an 8-bit counter that is incremented once every WDTCLK clock cycles. After
an external reset, the watchdog timer is disabled and all registers are set to zeros.
During the initialization period, CPU read the WDTENB and WDTM[3:0] in information block.
WDTENB is the disable bit. When this bit is high, the watchdog function will be disabled. The
WDTM[3:0] is to set the frequency division for WDTCLK as shown in the figure below. User can to
set WDTENB and WDTM[3:0] through the writer.
WDTCLK =
Fosc
12X 2^WDTM
Watchdog reset time = ²⁵⁶
WDTCLK
Once the watchdog is started it cannot be stopped. User can refreshed the watchdog timer to zero
when WDTK register is written by 55h.
When Watchdog timer is overflow, the WDTF flag will set to one and automatically reset MCU. The
WDTF flag can be clear by software or external reset.
The watchdog timer must be refreshed regularly to prevent reset request signal from becoming
active.
Fig. 10-1: Watchdog timer block diagram
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
39
Ver.B SM59R16A2/SM59R08A2 06/2009