SM59R16A2 Datasheet, PDF (27/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
7.1 Timer/counter mode control register (TMOD)
Mnemonic: TMOD
7
6
5
GATE C/T
M1
Timer 1
Address: 89h
4
3
2
1
0 Reset
M0 GATE C/T
M1
M0 00h
Timer 0
GATE: If set, enables external gate control (pin INT0 or INT1 for Counter 0 or 1,
respectively). When INT0 or INT1 is high, and TRx bit is set (see TCON
register), a counter is incremented every falling edge on T0 or T1 input pin
C/T: Selects Timer or Counter operation. When set to 1, a counter operation is
performed, when cleared to 0, the corresponding register will function as a
timer.
M[1:0]: Selects mode for Timer/Counter 0 or Timer/Counter 1.
M1 M0 Mode
Function
00
Mode0 13-bit counter/timer, with 5 lower bits in TL0 or
TL1 register and 8 bits in TH0 or TH1 register
(for Timer 0 and Timer 1, respectively). The 3
high order bits of TL0 and TL1 are hold at zero.
01
Mode1 16-bit counter/timer.
10
Mode2 8 -bit auto-reload counter/timer. The reload
value is kept in TH0 or TH1, while TL0 or TL1 is
incremented every machine cycle. When TLx
overflows, a value from THx is copied to TLx.
11
Mode3 If Timer 1 M1 and M0 bits are set to 1, Timer 1
stops. If Timer 0 M1 and M0 bits are set to 1,
Timer 0 acts as two independent 8 bit timers /
counters.
7.2 Timer/counter control register (TCON)
Mnemonic: TCON
7
6
5
4
3
TF1 TR1 TF0 TR0
IE1
Address: 88h
2
1
0 Reset
IT1
IE0
IT0 00h
TF1: Timer 1 overflow flag set by hardware when Timer 1 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR1: Timer 1 Run control bit. If cleared, Timer 1 stops.
TF0: Timer 0 overflow flag set by hardware when Timer 0 overflows. This flag can
be cleared by software and is automatically cleared when interrupt is
processed.
TR0: Timer 0 Run control bit. If cleared, Timer 0 stops.
IE1: Interrupt 1 edge flag. Set by hardware, when falling edge on external pin INT1
is observed. Cleared when interrupt is processed.
IT1: Interrupt 1 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
IE0: Interrupt 0 edge flag. Set by hardware, when falling edge on external pin INT0
is observed. Cleared when interrupt is processed.
IT0: Interrupt 0 type control bit. Selects falling edge or low level on input pin to
cause interrupt.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
27
Ver.B SM59R16A2/SM59R08A2 06/2009