SM59R16A2 Datasheet, PDF (48/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
14 IIC function
As most of the IIC we have been familiar with, this IIC module uses the SCL (clock) and the SDA
(data) line to communicate with the other IIC interfaces. Its speed can be selected up to 400Kbps
(maximum) by software setting the SFR IICBR[2:0]. The IIC module can be either master or slave,
provided two interrupts (RXIF, TXIF), and has two addresses for data transmission. It will generate
START, repeated START and STOP signals automatically in master mode and can detects START,
repeated START and STOP signals in slave mode. The maximum communication length and the
number of devices that can be connected are limited by a maximum bus capacitance of 400pF.
SM59R16A2/SM59R08A2 IIC function is fully compatible to most of the other chips’. So there is no
barrier in the mutual communication.
Mnemonic Description
IICCTL
IICS
IICA1
IICA2
IICRWD
IIC control
register
IIC status register
IIC Address 1
register
IIC Address 2
register
IIC Read/Write
register
Direct
F9h
F8h
FAh
FBh
FCh
Bit 7
IICEN
MStart
Bit 6 Bit 5 Bit 4 Bit 3
IIC function
BF MSS MAS RStart
RXIF TXIF RDR TDR
IICA1[7:1]
Bit 2
RXAK
IICA2[7:1]
IICSRWD[7:0]
Bit 1
Bit 0
IICBR[2:0]
TXAK
RW
MATCH1
or RW1
MATCH2
or RW2
RESET
04h
00h
A0h
60h
00h
Mnemonic: IICCTL
7
6
5
IICEN BF MSS
4
3
MAS RStart
Address: F9h
2
1
0
Reset
IICBR[2:0]
04h
IICEN: Enable IIC module
IICEN = 1 is Enable
IICEN = 0 is Disable.
BF: Bus failed flag (used in master mode only)
When the module is transmitting a “1” to SDA line but detected as a “0” from SDA line in master
mode, it is called as arbitration loss. This bit can be cleared by software.
MSS: Master or slave mode select.
MSS = 1 is master mode.
MSS = 0 is slave mode.
*The software must set this bit before setting others register.
MAS: Master address select (master mode only)
MAS = 0 is to use IICA1.
MAS = 1 is to use IICA2.
RStart: Re-start control bit (master mode only)
When this bit is set, the module will generate a start condition to the SDA and SCL lines (after
current ACK) and send out the calling address which is stored in either IICA1 or IICA2 (selected
by MAS control bit). After the address is sent out, this bit will be cleared by hardware.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
48
Ver.B SM59R16A2/SM59R08A2 06/2009