SM59R16A2 Datasheet, PDF (24/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
6.1.2 Second phase: executing calculation.
During executing operation, the MDU works on its own parallel to the CPU. When MDU is finished,
the MDUF register will be set to one by hardware and the flag will be cleared at the next calculation.
Mnemonic: PCON
7
6
5
4
3
SMOD MDUF -
PMW
-
Address: 87h
2
1
0
Reset
-
STOP IDLE 00h
MDUF: MDU finish flag.
When MDU is finished, the MDUF will be set by hardware and the bit will clear
by hardware at next calculation.
The following table gives the execution time in every mathematical operation.
Operation
Division 32bit/16bit
Division 16bit/16bit
Multiplication
Shift
Normalize
Table 6-2: MDU execution times
Number of Tclk
17 clock cycles
9 clock cycles
11 clock cycles
Min. 3 clock cycles, Max. 18 clock cycles
Min. 4 clock cycles, Max. 19 clock cycles
6.1.3 Third phase: reading the result from the MDx registers.
The sequence of reading out the first MDx registers is not critical, but we have to be aware that the
last read (from MD5 in division operation, or MD3 by multiplication, shift and normalizing) means the
end of a whole calculation.
Table 6-3: MDU registers read sequence
Operation
32Bit/16Bit
16Bit/16Bit
16Bit x 16Bit
shift/normalizing
First read MD0 Quotient Low MD0 Quotient Low
MD0 Product Low MD0 LSB
MD1 Quotient
MD1 Quotient High
MD1 Product
MD1
MD2 Quotient
MD2 Product
MD2
MD3 Quotient High
MD4 Remainder L MD4 Remainder Low
Last read MD5 Remainder H MD5 Remainder High MD3 Product High MD3 MSB
Here the operation of normalization and shift will be explained more. In normalization, all reading
zeroes in registers MD0 to MD3 are removed by shift left. The whole operation is completed when
the MSB (most significant bit) of MD3 register contains a ’1’. After normalizing, bits ARCON.4 (MSB)
to ARCON.0 (LSB) contain the number of shift left operations. As for shift, SLR bit (ARCON.5) has
to contain the shift direction, and ARCON.4 to ARCON.0 represent the shift count (which must not be
0). During shift, zeroes come into the left or right end of the registers MD0 or MD3, respectively.
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
24
Ver.B SM59R16A2/SM59R08A2 06/2009