SM59R16A2 Datasheet, PDF (49/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
IICBR[2:0]: Baud rate selection (master mode only), where Fosc is the external crystal or oscillator
frequency. The default is Fosc/512 for users’ convenience.
IICBR[2:0]
Baud rate
000
Fosc/32
001
Fosc/64
010
Fosc/128
011
Fosc/256
100
Fosc/512
101
Fosc/1024
110
Fosc/2048
111
Fosc/4096
Mnemonic: IICS
7
6
5
MStart RxIF TxIF
4
RDR
3
2
1
TDR RxAK TxAK
Address: F8h
0
Reset
RW 00h
MStart: Master start control bit (master mode only)
If this bit is set, the module will generate a start condition to the SDA and SCL lines, and send out
the calling address which is stored in either IICA1 or IICA2 (selected by MAS control bit). After
software clears this bit, the module will generate a stop condition to the SDA and SCL.
RxIF: Data receive interrupt flag
It is set after the IICRWD (IIC read /write data buffer) is loaded with a newly receive data. After
software clears this bit, the IICIF（IIC interrupt flag）will cleared.
TxIF: Data transmit interrupt flag
It is set when all the 8 bits in the shift register are transmitted, the 8 bits are from IICRWD (IIC
read /write data buffer) downloaded into the shift register. After software clears this bit, the IICIF
（IIC interrupt flag）will cleared.
RDR: Read data ready
It is set to high by hardware when a new byte is received and stored in IICRWD. The software
must clear this bit after it gets the data from IICRWD. The IIC module is able to write new data
into IICRWD only when this bit is cleared.
TDR: Transmit data ready
After putting the data into IICRWD in transmission, the software needs to set this bit to ‘1’ to
inform the IIC module to send the data out. After IIC module finishes sending the data from
IICRWD, this bit will be cleared automatically.
RxAK: Receive acknowledgement
This is a read-only bit judged by the transmitting side only.
If the IIC module is in the master mode : after it transmits the 8-bit data to the slave side, the slave
side will returned RxAK
= 0 : the slave receives the data successfully
= 1 : the slave fails to receive the data
If the IIC module is in the slave mode : after it sends the 8-bit data to the master side, the master
side will returned RxAK
= 0 : the master receives the data successfully(in some application, it may be that the master
wants more data)
= 1 : the master fails to receive the data (in some applications, it may be that the master does not
want any more data)
TxAK: Transmit acknowledgement
It is the corresponding bit of RxAK in the receiving side. It represents the receiving status as
explained in RxAK. Actually, it is sent as the 9^th bit in one byte transmission as show in Fig. 14-1.
RW: Slave mode read or write
It is a read-only bit used in slave mode only. It is from Bit 0 of IICA1 or IICA2 of the master side
as described below
= 0 : master asks this IIC module (in slave mode) to receive data (read)
=1 : master asks this IIC module (in slave mode) to transmit data (write)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
49
Ver.B SM59R16A2/SM59R08A2 06/2009