SM59R16A2 Datasheet, PDF (43/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Interrupt request register(IRCON)
Mnemonic: IRCON
Address: C0h
7
6
5
4
3
2
1
0
Reset
EXF2 TF2 IICIF
-
EEIIF ADCIF SPIIF
00h
EXF2: Timer 2 external reload flag, must be cleared by software.
TF2: Timer 2 overflow flag, must be cleared by software.
IICIF: IIC interrupt flag must be cleared after the RxIF and TxIF at IICS register clear by software。
EEIIF: EEI interrupt flag, must be cleared by software.
ADCIF: A/D converter interrupt flag, must be cleared by software
SPIIF: SPI interrupt flag, must be cleared by software.
11.1 Priority level structure
All interrupt sources are combined in groups:
Table 11-2: Priority level groups
Groups
External interrupt 0
Serial channel 1 interrupt
Timer 0 interrupt
-
External interrupt 1
-
Timer 1 interrupt
-
Serial channel 0 interrupt
-
Timer 2 interrupt
-
-
SPI interrupt
ADC interrupt
EEI interrupt
-
IIC interrupt
Each group of interrupt sources can be programmed individually to one of the four priority levels by
setting or clearing one bit in the SFRs IP0 and IP1. If requests of the same priority level is received
simultaneously, an internal polling sequence determines which request is serviced first.
Mnemonic: IP0
7
6
-
-
5
IP0.5
4
IP0.4
3
IP0.3
2
IP0.2
1
IP0.1
Address: A9h
0 Reset
IP0.0 00h
Mnemonic: IP1
7
6
-
-
5
IP1.5
4
IP1.4
3
IP1.3
2
IP1.2
1
IP1.1
Address: B9h
0 Reset
IP1.0 00h
Table 11-3: Priority levels
IP1.x IP0.x
Priority Level
0
0
Level0 (lowest)
0
1
Level1
1
0
Level2
1
1
Level3 (highest)
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
43
Ver.B SM59R16A2/SM59R08A2 06/2009