SM59R16A2 Datasheet, PDF (50/67 Pages) SyncMOS Technologies,Inc – 8-Bit Micro-controller

SM59R16A2/SM59R08A2
8-Bit Micro-controller
64KB/32KB ISP Flash & 2KB RAM embedded
Fig. 14-1: Acknowledgement bit in the 9^th bit of a byte transmission
Mnemonic: IICA1
Address: FAh
7
6
5
4
3
2
1
0
Reset
IICA1[7:1]
Match1 or RW1 A0h
Slave mode:
IICA1[7:1]: IIC Address registers
This is the first 7-bit address for this slave module. It will be checked when an address (from
master) is received
Match1: When IICA1 matches with the received address from the master side, this bit will set to 1 by
hardware. When IIC bus is stopped, this bit will clear automatically.
Master mode:
IICA1[7:1]: IIC Address registers
This 7-bit address indicate the slave with which it want to communicate.
RW1: This bit will be sent out as RW of the slave side if the module has set the MStart or RStart bit. It
appears at the 8^th bit after the IIC address as shown in Fig. 14-2. It is used to tell the salve the
direction of the following communication. If it is 1, the module is in master receive mode. If 0, the
module is in master transmit mode.
Fig. 14-2: RW bit in the 8^th bit after IIC address
Specifications subject to change without notice contact your sales representatives for the most recent information.
ISSFD-M034
50
Ver.B SM59R16A2/SM59R08A2 06/2009