RM0029 Datasheet, PDF (89/1740 Pages) STMicroelectronics – The primary objective of this document

RM0029
Introduction
1.4.20
1.4.21
1.4.22
and four independent timer comparators. These comparators produce a CPU interrupt when
the timer exceeds the programmed value.
The following features are implemented in the STM:
● One 32-bit up counter with 8-bit prescaler
● Four 32-bit compare channels
● Independent interrupt source for each channel
● Counter can be stopped in debug mode
Software watchdog timer (SWT)
The Software Watchdog Timer (SWT) is a second watchdog module to complement the
standard Power Architecture watchdog integrated in the CPU core. The SWT is a 32-bit
modulus counter, clocked by the system clock or the crystal clock, that can provide a system
reset or interrupt request when the correct software key is not written within the required
time window.
The following features are implemented:
● 32-bit modulus counter
● Clocked by system clock or crystal clock
● Optional programmable watchdog window mode
● Can optionally cause system reset or interrupt request on timeout
● Reset by writing a software key to memory mapped register
● Enabled out of reset
● Configuration is protected by a software key or a write-once register
Cyclic redundancy check (CRC) module
The CRC computing unit is dedicated to the computation of CRC off-loading the CPU. The
CRC features:
● Support for CRC-16-CCITT (x25 protocol):
– X¹⁶ + X¹² + X⁵ + 1
● Support for CRC-32 (Ethernet protocol):
– X³² + X²⁶ + X²³ + X²² + X¹⁶ + X¹² + X¹¹ + X¹⁰ + X⁸ + X⁷ + X⁵ + X⁴ + X² + X + 1
● Zero wait states for each write/read operations to the CRC_CFG and CRC_INP
registers at the maximum frequency
Error correction status module (ECSM)
The ECSM provides a myriad of miscellaneous control functions regarding program-visible
information about the platform configuration and revision levels, a reset status register, a
software watchdog timer, wakeup control for exiting sleep modes, and information on
platform memory errors reported by error-correcting codes and/or generic access error
information for certain processor cores.
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