RM0029 Datasheet, PDF (1677/1740 Pages) STMicroelectronics – The primary objective of this document

RM0029
JTAG Controller (JTAGC)
Table 940. Device identification register field descriptions (continued)
Field
Description
21–12
PIN
Part Identification Number
Bits [21:12] contain the part number of the device.
11–1
MIC
Manufacturer’s Identification Code
Bits [11:1] contain the JEDEC (Joint Electron Device Engineering Council) manufacturer’s
identification code.
Bit [0]
IDCODE Register ID
Bit [0] identifies this register as the device identification register and not the bypass
register
CENSOR_CTRL Register
The CENSOR_CTRL register is a 64-bit shift register path from TDI to TDO selected when
the ENABLE_CENSOR_CTRL instruction is active. The default reset value of the
CENSOR_CTRL register is 64’b0. The CENSOR_CTRL register transfers its value to a
parallel hold register on the rising edge of TCK when the TAP controller state machine is in
the Update-DR state. Once the ENABLE_CENSOR_CTRL instruction is executed, the
register value will remain valid until a JTAG reset occurs.
*⁽¹⁾
...
2
1
0
R
CENSOR_CTRL
W
Reset:
*⁽²⁾
*
*
*
*
1. The size of CENSOR_CTRL is 64 bits.
2. The reset value of CENSOR_CTRL is 64’b0.
Figure 1012.CENSOR_CTRL Register
Table 941. CENSOR_CTRL register field descriptions
Field
Description
63–0
CENSOR_CTRL
[63:0]
Censorship Control
The CENSOR_CTRL bits are used to control chiptop censorship functions.
Boundary Scan Register
The boundary scan register is connected between TDI and TDO when the EXTEST,
SAMPLE or SAMPLE/PRELOAD instructions are active. It is used to capture input pin data,
force fixed values on output pins, and select a logic value and direction for bidirectional pins.
Each bit of the boundary scan register represents a separate boundary scan register cell, as
described in the IEEE 1149.1-2001 standard and discussed in Section 36.5.5, Boundary
scan. The size of the boundary scan register and bit ordering is device-dependent.
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