RM0029 Datasheet, PDF (1332/1740 Pages) STMicroelectronics – The primary objective of this document

Deserial Serial Peripheral Interface (DSPI)
RM0029
SCK
(CPOL = 0)
Master SOUT
PCS
1 LSB
Command Frame
Active Phase
t_DT = from 1 to 64 T_SCK
Command Frame = 4 to 32 bits
Data Frame = 4 to 32 bits
Data Frame
Active Phase
Invalid
0 ^LSB
Invalid
t_DT
t_DT
Selection Bit
Figure 756. TSB Downstream frames
Figure 756 shows the two types of MSC downstream frames: command frame and data
frame.
The first transmitted bit, called the selection bit, determines the frame type:
● The selection bit “0” indicates a data frame
● The selection bit “1” indicates a command frame
Data frame may contain up to two selection bits to support two external slave devices, (so
called dual receiver configuration) or no selection bits at all.
The command frame can be written by software, through SPI TX FIFO, using one or two
FIFO entries with help of the CONT bit. The data frame consists of up to 32 bits from the
DSPI_SDR or DSPI_ASDR registers and up to two zero selection bits. The number of data
bits in the data frame is defined by field DSPI_DSCICR1[TSBCNT].
The selection bit of the MSC command frames (1) can be implemented by software.
To comply with MSC specification, set DSPI_CTARn[LSBFE] to transmit the least significant
bit first.
Regardless of the LSBFE bit setting, the Data Frame Selection Bits, if enabled, are always
transmitted first, before the corresponding data subframes.
MSC dual receiver support with PCS switchover
When in TSB mode it is possible to switch the set of PCS signals that are driven during the
first part of the frame to a different set of PCS signals during the second part of the frame.
The bit, at which this switchover occurs, is defined by field FMSZ of the DSPI_CTARn
register, which is selected by field DSPI_DSICR[DSICTAS].
Number of the bits, not including the Data Selection Bit, in the first part of the frame is equal
to value of the FMSZ field plus one. During this part of the frame the PCS signal levels are
controlled by DSPI_DSICR DPCSn bits, after that by DSPI_DSICR1 DPCS1_n bits.
The PCS switchover occurs at driving edge of the SCK clock output.
The second Data Selection Bit is inserted after the PCS switchover if enabled.
1332/1740
Doc ID 15177 Rev 8