RM0029 Datasheet, PDF (1408/1740 Pages) STMicroelectronics – The primary objective of this document

FlexCAN Module
RM0029
f_OSC
f_SYS
N = No. of Message Buffers Implemented
FlexCAN A: N = 64
FlexCAN B: N = 64
FlexCAN C: N = 64
T_q
Divider
CR[CLKSRC]
CR[PRESDIV]
MCR[MDIS]
Control and
Status Registers
CAN Engine
VDDEHx
CR[LPB | LOM]
Tx Shifter
Protocol
Engine
Rx Shifter
Wake up
detection
1
0
CR[LPB]
MCR[SLF_WAK]
TIMER
Timer
16 bit free running timer Reset ^{Synchronization}
CR[TSYN]
Interrupts
Message Buffers (MB)
MB 0
0 1 MCR[FEN]
IMRH | IMRL[BUFFxM]
N
N
Message Buffer
1
N
MB 8
CR[BOFFMSK]
1
CR[ERRMSK]
1
CR[TWRNMSK]
1
CR[RWRNMSK]
1
MCR[WAK_MSK]
1
Bus Off
Error
Tx Warning
Rx Warning
Wake up
MB N-1
Notes:
1: Pins can be configurable. Check device system configuration
2: Check interrupt controller which interrupts have been used
and regrouped. Interrupts can be additionally enabled/disabled
in the interrupt controller
3: Please check device system configuration for further clock divider,
muxing and low power configuration. See the section for the
SIU_SYSDIV[CAN 2:1] for the additional system clock pre-
divider.
Figure 807. FlexCAN block diagram
1408/1740
Doc ID 15177 Rev 8