RM0029 Datasheet, PDF (201/1740 Pages) STMicroelectronics – The primary objective of this document

RM0029
Enhanced Direct Memory Access Controller (eDMA)
eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the
TCD of the given channel. The data value on a register write causes the DONE bit in the
corresponding transfer control descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a
global clear function, forcing all DONE bits to be cleared.
If bit 0 is set, the CDSB command is ignored. This allows multiple byte registers to be written
as a 32-bit word. Reads of this register return all zeroes.
Figure 33. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Offset: EDMA_BASE + 0x001F
Access: User write-only
0
1
2
3
4
5
6
7
R
W NOP
CDSB[0:6]
Reset 0
0
0
0
0
0
0
0
Table 35. EDMA_CDSBR field descriptions
Field
Description
NOP
No operation
0 Normal operation
1 No operation, ignore bits 1–7.
CDSB[0:6]
Clear DONE Status Bit
0–32 (64 for eDMA) Clear the corresponding channel’s DONE bit.
64–127
Clear all TCD DONE bits.
eDMA Interrupt Request Registers (EDMA_IRQRH, EDMA_IRQRL)
The EDMA_IRQRH and EDMA_IRQRL provides a bitmap for the 32 channels signaling the
presence of an interrupt request for each channel. EDMA_IRQRH maps to channels 63–32
and EDMA_IRQRL maps to channels 31–0.
The DMA engine signals the occurrence of a programmed interrupt on the completion of a
data transfer as defined in the transfer control descriptor by setting the appropriate bit in this
register. The outputs of this register are directly routed to the interrupt controller (INTC).
During the execution of the interrupt service routine associated with any given channel,
software must clear the appropriate bit, negating the interrupt request. Typically, a write to
the EDMA_CIRQR in the interrupt service routine is used for this purpose.
The state of any given channel’s interrupt request is directly affected by writes to this
register; it is also affected by writes to the EDMA_CIRQR. On writes to the EDMA_IRQRH
or EDMA_IRQRL, a 1 in any bit position clears the corresponding channel’s interrupt
request. A 0 in any bit position has no effect on the corresponding channel’s current
interrupt status. The EDMA_CIRQR is provided so the interrupt request for a single channel
can be cleared without performing a read-modify-write sequence to the EDMA_IRQRH and
EDMA_IRQRL.
Doc ID 15177 Rev 8
201/1740