RM0029 Datasheet, PDF (67/1740 Pages) STMicroelectronics – The primary objective of this document

RM0029
1
Introduction
Introduction
1.1
The SPC564A74xx, SPC564A80xx Microcontroller Family
The SPC564A74xx, SPC564A80xx is part of a family of microcontrollers that serves two
main application areas:
● Mid-range engine management
● Automotive transmission control
The SPC564A74xx, SPC564A80xx contains features of ST’s SPC563M family and many
new features coupled with high performance 90 nm CMOS technology to provide
substantial reduction of cost per feature and significant performance improvement.
The e200z4 host processor core of the SPC564A74xx, SPC564A80xx complies with the
Power Architecture^® embedded category architecture. It is 100% user mode compatible
(with floating point library) with the classic PowerPC instruction set. In addition to the Power
Architecture instruction set, this core also has additional instruction support for digital signal
processing (DSP).
The SPC564A74xx, SPC564A80xx has two levels of memory hierarchy consisting of 8 KB
of instruction cache, backed by up to 192 KB on-chip SRAM and up to 4 MB of internal flash
memory. The SPC564A74xx, SPC564A80xx includes an external bus interface and a
“calibration bus” that is only accessible when using calibration tools.
On-chip modules include:
● Dual issue, 32-bit Power Architecture embedded category compliant e200z4 CPU core
complex
● Memory protection unit (MPU)
● Interrupt controller (INTC)
● Frequency-modulated phase-locked loop (FMPLL)
● System integration unit (SIU)
● Boot assist module (BAM)
● 32-channel second generation enhanced time processor unit (eTPU2)
● 24-channel enhanced modular Input Output System (eMIOS)
● Enhanced queued analog-to-digital converter (eQADC)
● 3 deserial serial peripheral interface (DSPI) modules
● 3 enhanced serial communication interface (eSCI) modules
● 3 controller-area network (FlexCAN) modules
● Cyclic redundancy check (CRC) module
● System timers
● Nexus development interface (NDI) per IEEE-ISTO 5001-2003 and 2010 standards
● On-chip voltage regulator for regulating 5 V down to 3.3 V for internal functions and
Nexus interface
● On-chip voltage Regulator controller for regulating 5 V down to 1.2 V for core logic
Doc ID 15177 Rev 8
67/1740